Lecture_42 - inverter's load capacitance C L v I v O v C v...

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EE 310 Lecture 42 Noise Immunity of CMOS Logic How much noise can be added before causing bit errors? Lecture 42 Page 1
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Finding V IL , V IH Values Let K n = K p and V TN = − V TP for symmetry. PMOS Region of operation: NMOS Region of operation: EE 310 Lecture 42 Lecture 42 Page 2
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Noise Margin Definitions EE 310 Lecture 42 Lecture 42 Page 3
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Example Find the two noise margins for a 74HC04 CMOS Inverter: V DD = 5 V, K p = K n , V TP = −1 V, V TN = 1 V EE 310 Lecture 42 Lecture 42 Page 4
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Speed and Propagation Delay It takes a finite amount of time to charge and discharge the
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Unformatted text preview: inverter's load capacitance C L v I v O v C v I t v C t v O t Propagation Delay: For clocked logic, t p can't exceed half the clock period: EE 310 Lecture 42 Lecture 42 Page 5 Example The clock rate in a microprocessor is 3.2 GHz. Find the maximum permissible propagation delay: EE 310 Lecture 42 Lecture 42 Page 6 Propagation Delay in CMOS Logic EE 310 Lecture 42 Lecture 42 Page 7 Propagation Delay in CMOS Logic (Continued) EE 310 Lecture 42 Lecture 42 Page 8...
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This note was uploaded on 10/12/2010 for the course E E 310 at Pennsylvania State University, University Park.

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Lecture_42 - inverter's load capacitance C L v I v O v C v...

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