Lecture_43 - 5. Pull-Up Network Pull-Down Network V DD Y A...

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EE 310 Lecture 43 CMOS Logic -- NOR Gates Truth Table: A B Y 0 0 0 1 1 0 1 1 A B Y Y = A + B Mechanical Switch Analogy: Circuit: Lecture 43 Page 1
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CMOS Logic -- NAND Gates Truth Table: A B Y 0 0 0 1 1 0 1 1 Mechanical Switch Analogy: Circuit: A B Y Y = A • B EE 310 Lecture 43 Lecture 43 Page 2
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Transistor Sizing Considerations A B Y Y = A + B V DD Y A B A B Y Y = A B Y A B EE 310 Lecture 43 Lecture 43 Page 3
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Synthesis of Arbitrary Logic Functions Express Y in terms of inputs A, B, C 1. OR requires two devices in parallel AND requires two devices in series Synthesize the Pull-Down Network directly, in NMOS 2. Obtain the Pull-Up Network by applying DeMorgan’s theorem to the PDN 3. Synthesize the Pull-Up Network in PMOS 4. Add an inverter on the output to obtain Y
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Unformatted text preview: 5. Pull-Up Network Pull-Down Network V DD Y A B C A B C EE 310 Lecture 43 Lecture 43 Page 4 Example Pull-Up Network Pull-Down Network V DD Y A B C A B C Synthesize Y = AB + C(D+E) Example: EE 310 Lecture 43 Lecture 43 Page 5 Example (Continued) Pull-Up Network Pull-Down Network V DD Y A B C A B C For the Pull-Up Network, synthesize the complement of Y = AB + C(D+E) Example (Continued): EE 310 Lecture 43 Lecture 43 Page 6 Final Circuit Solution to Y = AB + C(D+E) Add an inverter to get Y as the output EE 310 Lecture 43 Lecture 43 Page 7...
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This note was uploaded on 10/12/2010 for the course E E 310 at Pennsylvania State University, University Park.

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Lecture_43 - 5. Pull-Up Network Pull-Down Network V DD Y A...

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