EE 332 Lesson 0719 - 7/19/2010 AMPLIFIER GAINS ii Ro vi Ri...

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7/19/2010 1 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock EE 332 DEVICES AND CIRCUITS II WEEK 5 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock AMPLIFIER GAINS R o A R L Source Control component Load i i R s v o o v i o i i o L o i i i v A v i A i v R i v R i Basic gains: o o i v i i L i i i v v v A R A R i v i i o v i R i 9 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock CE AMPLIFIER (INVERTING) WITH BYPASS CAPACITOR/ SMALL SIGNAL MODEL R s v S C1 R 2 R 1 R C R E Q1 C2 C3 V CC R L v o v o v s R 2 R 1 R C R L r r o g m v be v be R s 10 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock CE AMPLIFIER (INVERTING) WITH BYPASS CAPACITOR/ INPUT & OUTPUT RESISTANCES v o v s R 2 R 1 R C R L r r o g m v be v be R s Input resistance: 12 / / / / / / / / CE ib b CE i R R R r and rr R R R r  Output resistance: // CE o c C co CE o o C C R r R and R r R R r b r c 11 ©UW EE TC Chen
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This note was uploaded on 10/12/2010 for the course IT 23211 taught by Professor Tai during the Summer '10 term at Punjab Engineering College.

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EE 332 Lesson 0719 - 7/19/2010 AMPLIFIER GAINS ii Ro vi Ri...

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