EE 332 Lesson 0804 - 8/4/2010 OPERATIONAL AMPLIFIER DESIGN...

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8/4/2010 1 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock EE 332 DEVICES AND CIRCUITS II WEEK 7 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock OPERATIONAL AMPLIFIER DESIGN / INTRODUCTION Typical Operational Amplifier Topology _ + Differential input stage (high gain) Single-ended second gain stage (high gain) Low-gain low impedance output stage Note: This assumes that the output is taken differential as we get v od /2 on the output and v od /2 on the other. In other words, if we only use one output we lose half of the total gain 6 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock DIFFERENTIAL AMPLIFIERS / COMMON-MODE REJECTION RATIO Want a differential amplifier to amplify v id , but v ic → Want the differential amplifier to reject the common - mode input 2 2 vd m C C vc E Em A g R CMRR R A R CMRR R g   Common-mode rejection ratio (CMRR): the ratio between signal gain to noise gain 7 ©UW EE TC Chen Microelectronic Circuit Design Jaeger/Blalock
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EE 332 Lesson 0804 - 8/4/2010 OPERATIONAL AMPLIFIER DESIGN...

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