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# hw10 - Fall 2007 Due 7 December 2007 Section A B RPY ECE...

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Unformatted text preview: Fall 2007 Due: 7 December, 2007 Section A, B, RPY ECE 3060 Homework 10 VLSI and Advanced Digital Design Homework should be submitted at KACB 3318 by 4:30 PM. This homework is optional, and will replace your lowest HW grade if submitted. 1.Consider a standard cell library consisting of the following cells,: (l is the load on a given gate). For the minimum delay mappings, use load bins of 1, 2, 4, and 10. Cell INV SINV2 SINV4 NOR2 NAND2 OAI21 Area 3 6 10 7 5 7 Delay 1+l 1+0.5l 1+0.25l 2+2l 2+1.5l 3+2l Input load 1 2 4 2 1 2 (i) Using INV and NAND2 as base function, draw pattern trees of the cells in the library. (ii) Using INV and NAND2 as base function, draw the subject tree of f = ab(c + d) + be(a + c) . (iii) Find a minimum area mapping of f. (iv) Find a minimum delay mapping of f assuming a load of 2. (v) Find a minimum delay mapping of f assuming a load of 10. Note: Do not use SINV gates on the inputs to this circuit! ! ! !"!# \$%&'()*+!,-*!.%//%0(&1!',2,*!)(21+23# \$%&'()*+!,-*!.%//%0(&1!',2,*!)(21+23# state diagram: 2.Consider the following IPI 8I !8 Q IPN IPI NPN IPI 8I !8 Q IPN IPN PI !8 R N NP NPN N NPI NPI 8L IPI !8 R NPN NPN NPI NPI 8L IPI IPI NPN 8" !8 ? IPI NPN IPI8? 8" ! IPI 2# 2# 6# 4*+(5*!2!',2,*!,+2&'(,(%&!,26/*# (a) Derive a state transition table 6# 4+20!2&!789!:-2+,!.%+!;2+,!2<# 4*+(5*!2!',2,*!,+2&'(,(%&!,26/*# :# =*+.%+3!',2,*!3(&(3(>2,(%&!%&!;2+,!2<# as described in lecture. (b) Perform state minimization 4+20!2&!789!:-2+,!.%+!;2+,!2<# )# 4+20!2!',2,*!)(21+23!.%+!;2+,!:<# =*+.%+3!',2,*!3(&(3(>2,(%&!%&!;2+,!2<# :# (c) Draw the resulting state diagram if different !?! @%+!,-*!:(+:A(,!6*/%0B!!&)!2!C%%/*2&!*D;+*''(%&!.%+!,-*!'*,!%.!2//!,*','!,-2,!)*,*:,!,-*!.%//%0E )# # 4+20!2!',2,*!)(21+23!.%+!;2+,!:<# (&1!.2A/,'F 3. Consider @%+!,-*!:(+:A(,!6*/%0B!!&)!the following circuit: .%+!,-*!'*,!%.!2//!,*','!,-2,!)*,*:,!,-*!.%//%0E 2!C%%/*2&!*D;+*''(%&! 2A/,'F "I "I #I "Q "Q 2# 2# 6# :# )# "L (a) Find a test vector to detect a s-a-1 on x . #I ! ! "L 7G4!6+()1*!6*,0**&!(&;A,'!%.!12,*!HI# 3 6# JK!6+()1*!6*,0**&!DI!2&)!DL# 7G4!6+()1*!6*,0**&!(&;A,'!%.!12,*!HI# :# 8(&1/*!.2A/,!MDL!'E2ENO# (b) Find a test vector to detect a s-a-0 on the upper input to the gate labeled G1. JK!6+()1*!6*,0**&!DI!2&)!DL# )# 9A/,(;/*!.2A/,'!MDI!'E2ENB!DL!'E2EIO# 8(&1/*!.2A/,!MDL!'E2ENO# 9A/,(;/*!.2A/,'!MDI!'E2ENB!DL!'E2EIO# ...
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