sample3-schimmel - ECE 3060 Advanced Digital Design and...

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ECE 3060 Advanced Digital Design and VLSI Sample Final Exam 1. (25) Consider the function f = a(b + c) + d . a) (10) Draw a transistor schematic (switch network) for g. b) (10) Find an order in which inputs a, b, c, d can appear such that we end up with a com- pact layout with continuous lines of n-diff and p-diff and straight lines of poly. c) (5) Draw a stick diagram for the layout of your cell. Clearly label this diagram. 2. (25) Logical effort. a) (5) Calculate the logical effort g NAND3 of an NAND3 gate as a function of γ . Show the proto- type gate complete with transistor sizes. b) (5) Calculate the logical effort g OAI22 of an OAI222 gate as a function of γ . Show the pro- totype gate complete with transistor sizes. c) (5) Minimize the delay from the circuit input to z, assuming that the delay to all three loads should be about the same, and γ =2. Give the delay to drive z, the maximum delay to any load, and the dimensions of each transistor in the gate that drives z assuming
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This note was uploaded on 10/13/2010 for the course ECE 3060 taught by Professor Shimmel during the Fall '07 term at Georgia Institute of Technology.

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sample3-schimmel - ECE 3060 Advanced Digital Design and...

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