33531369-chapter6-ex-sol-pdf

33531369-chapter6-ex-sol-pdf - 1 Chapter 6 Problem Set...

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1 Chapter 6 Problem Set Chapter 6 PROBLEMS 1. [E, None, 4.2] Implement the equation X = (( A + B ) ( C + D + E ) + F ) G using complemen- tary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W / L = 2 and PMOS W / L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Solution Rewriting the output expression in the form X = ((A + B ) (C + D + E ) + F ) G = ((AB + CDE)F) + G allows us to build the pulldown network by inspection (parallel devices imple- ment an OR, and series devices implement an AND). The pullup network is the dual of the pulldown network. The plot shows sizes that meet the requirement - in the worst case, the output resistance of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMOS W/L=6. The worst case pull-up resistance occurs whenever a single path exists from the output node to Vdd. Examples of vectors for the worst case are ABCDEFG=1111100 and 0101110. The best case pull-up resistance occurs when ABCDEFG=0000000. The worst case pull-down resistance occurs whenever a single path exists from the out- put node to GND. Examples of vectors for the worst case are ABCDEFG=0000001 and 0011110. The best case pull-down resistance occurs when ABCDEFG=1111111. 2. Implement the following expression in a full static CMOS logic fashion using no more than 10 transistors: Solution A B F C D E G F G C D E A B X 2 4 12 12 12 8 8 12 12 24 24 24 24 24 Y AB (29 ACE ⋅⋅ DE DCB + ++ =
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2 Chapter 6 Problem Set The circuit is given in the next figure. 3. Consider the circuit of Figure 6.1. a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W / L = 4 and PMOS W / L = 8. Solution The logic function is : . The transistor sizes are given in the figure above. b. What are the input patterns that give the worst case t pHL and t pLH . State clearly what are the initial input patterns and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes. Solution The worst case t pHL happens when the internal node capacitances ( Cx2 and Cx3 ) are charged before the high to low transition. The initial states that can cause this are: ABCD=[1010, 1110, 0110]. The final state is one of: ABCD=[1011, 0111]. D A V DD Y A B E B D E C C Figure 6.1 CMOS combinational logic gate. A B V DD Y C D C A D B W/L=12 W/L=12 W/L=12 W/L=12 W/L=8 W/L=8 W/L=16 W/L=16 Cx2 Cx3 Cx1 Y AB + (29 CD =
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Digital Integrated Circuits - 2nd Ed 3 The worst case t pLH happens when Cx1 is charged before the low to high transition. The input pattern that can cause this is: ABCD=[0111] =>[0011]. c. Verify part (b) with SPICE. Assume all transistors have minimum gate length (0.25 μ m). Solution The two cases are shown below.
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This note was uploaded on 10/13/2010 for the course ECE 680 taught by Professor Qiliangli during the Spring '09 term at George Mason.

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33531369-chapter6-ex-sol-pdf - 1 Chapter 6 Problem Set...

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