Single-Cycle MIPS Enhancements a We wish to add the...

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CprE 381 Computer Organization and Assembly Level Programming Homework #6 Assigned: October 13 Due: October 27 (9:00am) [Note from Joe: This assignment is on the design of processor datapath and control and its impact on performance. You may find the first part relatively easy as you have already had to consider adding features to the single-cycle processor in order to complete your Project Part B. To simplify your effort for the required illustrations, I have included in HW-06.zip two of the figures from the text.] Reading: Patterson & Hennessy, Sections 4.1-4.4 1) Single-Cycle MIPS Enhancements (a) We wish to add the instruction jr (jump register) to the single-cycle datapath described in this chapter. Add any necessary datapaths and control signals to the single-cycle datapath of Figure 4.21 on page 326 and show the necessary additions to Figure 4.22 on page 327. (b) This question is similar to part a) except that we wish to add the instruction lui (load upper immediate), which is described in Section 2.10. (c) Consider the single-cycle datapath in Figure 4.21 on page 326. A friend is proposing to

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