94203w97 - CARLETON liNiY?ERSITY $2915 in ll 7“ ”...

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Unformatted text preview: CARLETON liNiY?ERSITY $2915 in ll 7“ ” mgmgsmu IEEE Carleton Winter ‘97 Final Exam DURATION: 3 No. 0f Students: Department Name a Course Number: Systems and Computer Engineering Course lnstructor(s; PrOfessor Pearce AUTHORIZID “(NOIAND- Closed book, no calculators. St udents MUST count the number of pages in this examination question paper before beginning to write. and report any discrepancy immediately to a proctor. This question paper has 7 pages. This examination question paper MAY be taken from the examination room. There are 5 questions worth a total of 90 marks. Answer all 5 questions in the provided answer booklets. Do not ask questions during the exam unless you think there is an error or omission. —m 20f? 1) Give short answers to the following. Be concise! a) [2 marks} Assuming that an ISR has been installed in the vector table, suggest two different ways that the ISR might be caused to execute. b) [3 marks] What is busy waiting, why is it undesirable, and what solution (studied in this course) is ofien used to eliminate busy waiting? c) [1 mark] Why would it be a bad thing to make a FAR call to a subroutine that has been defined with the PROC NEAR directive? d) [3 marks] Conditional jump instructions use a relative displacement to specify a target destination. What is the displacement relative to, and why do you think it is done this way? ' e) [2 marks] Suppose a first year student asked: “I’m going to take 94.203 next year, what was the 96/97 version of the course all about?”. In (approximately) 50 words, what would you answer? 0 [4 marks] In the context of interrupt-driven programming (as discussed in class): What is interference? Give a brief example of how interference might occur. 2) [20 marks] Suppose that (for some reason) a C program must compute absolute (20- bit) address values from 16-bit segment and offset values. Write a Turbo C compatible 8088 assembler subroutine that will perform the required computation. The Turbo C prototype for the subroutine is: .41 void absaddrs( unsigned int segm, offs; unsigned longint *addrsvalue ); The first two parameters (segm and offs) are 16—bit unsigned values; the third parameter is the address of an unsigned long integer (an unsigned long integer is a 32— bit unsigned integer, with the least significant word stored in the low-address word). The subroutine must combine segm and 0&5 correctly and store the resulting value in the specified longint. Technical Note: The SI-IL (shifi lefi) and SI-IR (shift right) instructions have two forms. Examples: SH]. destination,1 SI—IR destination, CL ; shifts destination lefi 1 bit ; shifis destination right by the count in CL In this question, ASSUIVIE that support fimctions with the following prototypes exist (do NOT be concerned with any implementation details for the fimctions). You may also assume that each of the fiJnctions takes less than I msec to execute. void display_clock( int hours, rains ); display_c]ock displays the clock with the hour hand at hours, and the minute hand at mins. void clear_clock ( void ); clear_clock displays the clock with no hour or minute hands. byte get_key( void ); get_key must only be called when a key is available from the keyboard controller. get_key reads the controller and returns the key value read. [Simplification] Assume that get_key filters (ignores) all data associated with any extended key codes (i.e_ do not be concerned with 2 byte codes). Furthermore, ASSUME that: (i) the initialization of the timer and keyboard controller is taken care of elsewhere, and (ii) the timer has been set up to interrupt regularly with a fi'equency of 20 Hz, and (iii) your ISR’s have been installed in the vector table, and (iv) the timer (R0) and keyboard (LRl) interrupts have been enabled at the PIC, and (v) successive interrupts from the keyboard never occur faster than 75 msec apart. The objective is to have the displayed clock hands advance every minute (while the clock is not paused). The direction that the hands advance (i.e. clockwise or counter- clockwise) depends on commands fiom the keyboard. Note that reversing the Assume that no other sofiware (including DOS) is running in the system. The following single key commands must be recognized from the keyboard: 2 = zero the clock should be reset to twelve o’clock r = reverse the clock hands should change the direction that they advance 'lEEE Carleton! 8) b) C) 4) p = pause g 2 go the clock should stop advancing the clock should start advancing from the currently displayed time [12 marks] Give C-iike pseudocode for appropriate timer and keyboard ISRs. [2 marks] Give appropriate initial values for any static/global variables used by the ISRs, [6 marks] Identity all critical regions in the ISRs, and briefly state: why they are critical and how you have protected them. In the following question, a description of two devices is given first, and then you are asked to design some software using the devices. Suppose that the devices connected to a PIC in an SUSS-based system (similar tthe ones used in the lab) include: a timing device on IR4, and a switch interface on 1R6. For this question, assume that the PIC has edge sensitive inputs, and that it recognizes rising edges (transitions from 0 to 1). Timing Device: The device implements a 16-bit, count-down, one—shot timer. The input signal (to the device) is a 1 kHz square wave. There are two operational modes: idle and counting. Idle mode: the input signal is passed through directly as the output signal (to the PIC): Counting mode: the output signal is held at O, and each rising edge (transition from 0 to 1) on the input signal causes the 16-bit counter value to be decremented by one: Once the 16—bit counter value reaches 0, the device automatically reverts to the idle mode, 6 There are 2, 8-bit ports associated with the device: Timer Control Register (write only): at port address 400 (hex) Bits 1 and O (the two least significant bits) in the register encode the following commands: sto Ireset: forces device into idle mode load count register: may only be issued in the idle mode — issuing while in counting mode ma have unredictable results start: forces device into countin; mode In values written to the control register, all bits other than bits 1 and 0 are ignored by the device. Timer Data Register (write only): at port address 401 (hex) The single 8-bit data register must be used to load the 16-bit counter. Following the issue of a load counter command to the control register, the first byte written to the data register will be loaded as the most significant byte of the counter, and the second byte written will be loaded as the least significant byte. Switch Interface Device: The switch interface device generates a rising edge output (to the PIC) on EVERY change in the switch signal (input to the device fi'om the switch, i.e. a rising edge is generated to the PIC each time the signal from the switch goes from 0 to 1 or fiom l to 0!). The connected switch is bouncy (recall assignment 2); however, it is safe to assume that for each change in the ON/OFF position of the switch, any associated bounce stops within 30 milliseconds. Also, assume that successive changes in the ON/OFF position (i.e. changes made by users) are never less than 100 msec apart. There is a single 8-bit (read-only) data register to read the current switch signal value. The data register is at port address 500 (hex). In the values read from the data register: bit 0 (least significant bit) reflects the value of the switch (0 = OFF, 1 = 0N) all other bits = 0. You are asked to design a switch abstraction that allows programs to treat the switch as a stable (i.e. non—bouncy) device. Your abstraction must not use polling to overcome the switch bounce problem. Your solution must use the switch interface and timer interrupts to maintain a sofiware variable that reflects the current switch position, Your abstraction must also provide a read_switch fimction that simply retums the value of the software variable (but does not access any I/O ports). When answering the following, you are asked for pseudocode-Iike descriptions, do not give C/C++ or assembler code unless you feel that it is the best way to describe your solution. [15 marks] For your solution, identify any shared variables and give a high-level algorithm for each of the following: the switch interface device ISR the timing device ISR the read_switch function b) I555 Carleton In your algorithms, be explicit about all hardware—level access (e. g. give all port addresses and values written to ports). {10 marks] Describe the initialization required by your solution. Be explicit about all hardware and system details involved. [10 marks] Consider a serial communication controller that is similar to, but different from, the one discussed in class and used in assignment 5. In this controller, there are only two sources of interrupts: Rx Data Ready, and Tx Holding Register Empty. The device also includes the following registers (bit 0 is the least significant bit of a register): Interrupt Enable Register: [ER (write only) bit 0 Rx Interrupt Enable (1 = enable, 0 = disable) bit 1 Tx Interrupt Enable (1 = enable, 0 = disable) bits 2 — 7 unused Interrupt Clear Register: ICR ( write only) bit 0 Clear Rx Interrupt (1 = clear, 0 = no affect) bit 1 Clear Tx Interrupt (1 = clear, 0 = no affect) bits 2 - 7 unused The controller is difi‘erent from the one discussed in class in that once an interrupt has been generated from one of the sources, the device will not generate another interrupt the Interrupt Clear Register. The documentation for the controller is very explicit in that enabling the Tx interrupt while the Tx Holding Register is empty will cause a TX interrupt to be generated; however, the documentation is ambiguous in that it does not say whether clearing the Tx interrupt while the Tx Holding Register is empty will cause another Tx interrupt to be generated immediately. You are asked to design a test program that will provide the necessary infonnation to resolve the ambiguity identified above. Your program may use only the serial controller interrupt (e. g. no timer interrupts). You may assume that the Tx Holding Register is empty when your program begins execution, and that the controller device interrupt is disabled at the PIC. Give pseudocode for the complete program (including any global variables and ISRs). With the exception of the values written to the [ER and ICR, do not be concerned with hardware details like exact I/O addresses, or which PIC input the device is connected to, etc.; but, be sure to include any statements in your pseudocode that would be required to deal with the PIC appropriately (i.e. state the intention of any PIC access, but don’t worry about the hexadecimal values read/written, or specific I/O addresses involved). Include a brief overview of how the program works (ie. what information the program will provide, and how the information is obtained). ...
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This note was uploaded on 10/15/2010 for the course SYSC 3600 taught by Professor John bryant during the Spring '08 term at Carleton CA.

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94203w97 - CARLETON liNiY?ERSITY $2915 in ll 7“ ”...

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