20100920_ADSD_L02 - 2010/10/2 Topology I YiChangLu...

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2010/10/2 1 Advanced Digital System Design Topology I Yi Chang Lu Topology Basics Bus Contention bus, token bus, token ring, backplane bus Dt/dd / t Data/address/control Multiplexed, non multiplexed Synchronous, asynchronous Arbitration Release when done/Release on request Centralized/distributed Split transaction
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2010/10/2 2 Topology Basics Bus Examples Gigaplane, Sun Ultra Enterprise X000 Server 2 68GB 256bdt 42b dd lit t 83 8 MHl 2.68GBps, 256b data, 42b address, split trans., 83.8 MHz clock DEC AlphaServer8X00 2.1 GBps, 256b data, 40b address, split trans., 100 MHz clock, 1ft wire SGI PowerPath 2 1.2GBps, 256b data, 40b address, 6b control, split trans., 47.5 MHz clock, 1ft wire HP9000 Multiprocessor Memory Bus 1 GBps, 128b data, 64b address, pipeline bus, 60MHz clock, 13 inch wire Topology Basics Direct Network Router based network: mesh, torus, hypercube, trees, cube connected cycle connected cycles Indirect network Switch based network: crossbar, blocking MIN, non blocking MIN Hybrid network
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2010/10/2 3 Topology Basics Network Topology Basics More Networks
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2010/10/2 4 Topology Basics Direct Network Examples Cray T3E, bidirectional 3 D torus, 14b in each direction, 375 MHz link speed 600 MBp per lin
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  • Spring '10
  • Yi‐ChangLu
  • Measuring network throughput, Goodput, Maximum Channel Load, Topology Basics, Myricom Myrinet, support regular/irregular topology

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20100920_ADSD_L02 - 2010/10/2 Topology I YiChangLu...

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