CMPE200_HW3_mArch_single

CMPE200_HW3_mArch_single - CMPE 200 HW#3 Dr. Donald Hung...

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1 CMPE 200 HW#3 Dr. Donald Hung Computer Engineering Department, San Jose State University __________________________________________________________________ Consider a simple single-cycle implementation of MIPS ISA shown on Page 3. The operation times for the major functional components for this processor are as follows: Component Latency (ns) Component Latency (ns) ALU 10 Memory (IM/DM) Read/Write 15 Adder 8 PC Register Read/Write 2 ALU Control (decoder) 2 Register File Read 7 Shifter 3 Register File Write 5 Main Control (decoder) 4 2-1 MUX 2 Sign/zero Extender 3 Logic (1 or more levels of gates) 1 In this design the clock cycle is determined by the longest possible path in the processor. The critical paths for the different instruction types that need to be considered are: R-type, LW (load-word), and SW (store-word). All instructions have the same instruction fetch and decode steps. The basic register-transfer actions of the instructions are: Fetch/Decode: Instruction IMEM[PC];
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CMPE200_HW3_mArch_single - CMPE 200 HW#3 Dr. Donald Hung...

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