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Unformatted text preview: xvlll Preface languages. It includes material from Chapter 3 in the third edition so that the complete MIPS architecture is now in a single chapter, minus the floating—point i structions. Chapter 3 is for readers intcrcstcd in constnlcting a datapath or in learning more about floatingpoint arithmetic, Some will skip chapter 3, either because they don‘t need it or because it is a rcview.Chaptc1 4 combines two chapr ters from the third edition to explain pipelined processors. Sections 4.1, 4.5. and 4.10 give overviews For those with a software focus. Those with a hardwarc focus, however, will find that this chapter presents core material; they may also, depend ing on their background, want to read Appendix c on logic design first. Chapter 6 on storage is critical to readers with a software focus, and should he read by others if time permits. The last chapter on multicorcs, multiprocessors, and clusters is mostly new content and should be read by everyone. The first goal was to make parallelism a first class citizen in this edition, it was a separate chapter on the CD in the last edition, The most obvious example 5 Chapter 7. In particular. this chapter introduces the Rooflinc performance model, and shows its value by evaluating four recent multicore architectures on two kernels, This model could prove to be as insightful for niulticorc microprocessors as the 3C5 model is for caches. Given the importance of parallelism, it wasn‘t wise to wait until the last Chapter to tall: about, so there is a section on parallelism in each of the preceding six chapters: I Chapter ]: Pal-allL-I'mii mill vaer. It shows how power limits have forced the industry to switch to parallelism, and why parallelism helps, I Chapter ’: Parallelism and Instructions: Synchronization. This section dis cusses locks for shared variables, specifically the MIPS instructions Load Linked and him: Conditional. I Cllnpter3: Parallelism mianmpttrcrArithmetic: Flaming-PaintAssucirili ly. This section discusses thc challenges of numerical precision and floating point calculations. I Chapter 4; parallelism and Advanced Ittstrtlmnnrlhvel parallelism. It covers advanced lLP—superscalar, speculation, VLlW, loop.unrolling, and COO—as well as the relationship between pipeline depth and power consumption. I Chapters.-rnml/clisrnandMunoi-yuiamrchi rc'ucltccahcrrore. itintroduces cohcrcncy, consistency, and snooping cache protocols. I Chapter 6: Parallelism and 1/0: Redundant Arrays of Inexpensive Disks. It describes RAH) as a parallel no system as well as a highly available ICO system. Prefac- XIX Chapter 7 concludes with reasons for optimism why this foray into parallelism should be morc successful than tho sc of the past. 1 am particularly excited about the addition of an appendix on Graphical Processing Units written by NVIDLA’s chief scientist, David Kirk, and chief archir leL‘t, luhn Nickolls. Appendix A is the first iii-depth description of GPUS, which is a new and interesting thrust in computer architecture. The appendix builds upon the parallel themes ofthis edition to present a style of computing that allows the programmer to think MIMD yet the hardware tries to execute in SlMD-stylc whenever possible. As GPUs are both inexpensive and widely available—they are even found in many laptopsiand their programming environments are freely availahlc, they provide a parallel hardware platform that many could experiment with. The 5chde goal was to streamline the book to make room for new material in parallelism. The first stcp was simply going through all the paragraphs accumulated over three editions with a fine-toothed comb to see if they were still necessary. The coarsergruined changes were the merging ofchaptcrs and dropping of topics. Marl: Hill suggested dropping the multicycle processor implementation and instead adding a multicyclc cache controller to the memory hierarchy chapter. This allowed the processor to be presented in a single chapter instead of two. enhancing the processor mate ’vil by omission. The performance material from a separate chapter in the third edition is now blended into the first chapter. The third goal was to improve the pedagogy of the hook. Chapter 1 is now meatier, including performance. integrated circuits, and power, and it sets the stage for the rest of the book. Chapters 2 and 3 were originally written in an evolutionary style, starting with a “single celled" architecture and ending up with the full MIPS architecture by tl end of Chapter 3. This leisurely style is not a good match to the modern reader. 5 edition merge. ll of the instruction set material for the integer instructro s into Chapter Zmlnaking Chapter 3 optional for many readers—and each section now stands on its own. The reader no longer needs to read all of the preceding sections. lIence, Chapter 2 is now even better as a reference than it was in prior editions. Chapter 4 works better since the processor is now a single chapter, as the niulticyclc implementation is a distraction today. Chapter 5 has a new section on building cache controllers, along with a new CD section containing the Verilog code for that cache. ‘l'he accompanying CDrROM introduced in the third edition allowed us to reduce the cost of the book by saving pages as well as to go into greater depth on topics that were of interest to some but not all readers. Alas, in our enthusiasm to save pages, readers sometimes found themselves going back and forth between the CD and book more often than they Liked. This should not be the case in this edition, Each chapter now has the Historical Perspectives section on the CD and four chapters also have one advanced material section on the CD. Additionally, all ...
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