H-CMP-history - 1 2 1(Invited Chemical Mechanical Polishing The Impact of a New Technology on an Industry Kathleen A Perry Obsidian Inc 47485

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Unformatted text preview: 1. 2 1 (Invited) Chemical Mechanical Polishing: The Impact of a New Technology on an Industry Kathleen A. Perry Obsidian, Inc. 47485 Seabridge Drive Fremont, CA 94538, USA Introduction Chemical Mechanical Polishing (CMP), a technology born in IBM Confidential culture, has remained true to it's heritage not only because of it’s significant competitive advantage, but because of the history of it’s birth in the semiconductor industry. In spite of this heritage, CMP has grown from it’s invention in 1984, to one of the fastest growing segments of the semiconductor equipment industry. In 1997 the growth rate of CMP equipment averaged 30% in comparison with the rest of the semiconductor equipment market. The factors that enabled this dynamic growth include both the technical advantages of CMP and the history of it’s development and subsequent spread into the industry. The growth of CMP technology has spawned new business and supplier networks as well as new fields of study. As the science of CMP evolves, it continues to borrow from several diverse technical fields and has created a new science within semiconductors. Driving Force for CMP Technology The driving force behind CMP technology was the need for planarization of multilevel metallization. In the early 1980’s, logic devices were growing from three levels of metallization to four levels. At the same time, DRAM dimensionswere shrinking and these smaller device dimensions required improved planarization. The two main process technologies that were available for planarization at the time were Spin-On Glass (SOG) and Resist Etchback (REB). Successful implementation of SOG required a thorough understanding of the curing characteristics of the glass and the remaining stability of the material. In general there was considerable variation in the expertise available in this technology. In some companies for example, the use of SOG was considered more of an art than a science. REB on the other hand was a well understood technology, but suffered from complexity, expensive extra masking steps 0—7803—4700—6/98/$1 0.00 © 1998 lEEE and the need for significant monitoring to insure control of defectivity. With defectivity being the major yield limiting factor for semiconductor devices, a technology that displayed substantial variations in defectivity was not considered ideal. Enter CMP, a technology which at first glance would appear to be a “dirty” technology. CMP involves a Si wafer being immersed in a solution of suspended particles, and being polished against a pad on it’s front side. Such physical contact with the device side of a wafer was unknown in the conventional world of semiconductors where high vacuum technology and plasma physics were the standard. Surprisingly however, CMP was not only able to planarize the front—side of a wafer surface, but served as a way to clean the front—side of a wafer surface, removing any particles or defects in the surface of the glass. The relative simplicity of polishing a wafer was extremely attractive once the shock of this “dirty technology” in the cleanroom wore off. The technical justification for CMP was planarization capability. However it was the fact that CMP consistently produced a cleaner surface in comparison with competing planarization technology that became the main driving force for CMP. CMP technology won out on the technology battlefield because of it’s reduced defectivity and the fact that it was as much a cleaning process as a planarization process. History of CMP Technology CMP was invented by semiconductor industry giant IBM. [1] The technology was developed at IBM East Fishkill, NY in the early 1980’s. IBM was looking for a planarization technology to expand its mainframe logic chip from three levels of metal to four. The ability to evaluate something as foreign as "polishing" of a semiconductor device wafer was probably facilitated by the depth of technology present at IBM East Fishkill. East Fishkill was a goldmine of semiconductor technology, with an on- site Si crystal growing facility and it’s own Si wafer polishing lab. The first device wafers were polished on Strasbaugh polishing tools which were being used to polish bare Si wafers. The later presence of Strasbaugh in the CMP tool market was directly linked to its use as a Si polishing tool at IBM. Soon the idea of polishing for planarization spread to IBM’s facility in Burlington, Vermont where the need for a four level metal CMOS logic chip and a 1998 Symposium on VLSI Technology Digest of Technical Papers dense two level metal DRAM chip was driving the need for planarization. The environment at IBM Burlington at the time was one of extreme cost consciousness that stemmed from its experience in having to compete in the DRAM market. IBM Burlington chose a different CMP tool supplier. Westech (now IPEC Planar) was chosen as the IBM Burlington CMP tool of record, and thus the other major player in CMP equipment was born. The CMP equipment market would be dominated for several years by the equipment companies chosen by IBM. In addition, IBM‘s choice of consumable suppliers has created suppliers that continue to dominate the industry. Cabot slurry and Rodel pads, once used for Si wafer polishing have continued to remain the standards in CMP consumables and only are now starting to be challenged by alternative technologies. Growth of CMP beyond IBM When IBM entered the PC market in 1983, it chose to rely on outside suppliers of semiconductor chips such as Intel and Micron Technology. These relationships prompted IBM to share it’s semiconductor technology. In 1987, IBM shared CMP technology with Intel as part of a technology exchange. A similar exchange was made with Micron in 1988. These agreements were executed with a level of confidentiality that could be expected from IBM. They allowed both Intel and Micron to develop strong internal programs in CMP, but did little to open up the understanding of CMP technology to the outside world. These companies did however start to drive the supplier infrastructure. The major opening up of CMP technology came with the transfer of IBM's 4 Megabit DRAM process to SEMATECH in 1988. IBM transferred this process as a show of support to SEMATECH, but was unwilling to share it’s CMP technology, which was a key part of the process. IBM gave little information to SEMATECH about its planarization process, but did include the name of tool supplier Westech. Thus began a series of projects sponsored by SEMATECH to understand this new technology. SEMATECH's early projects in CMP focused on basic understanding of what CMP was, and on the reliability of Westech's polishing tool. In 1992, SEMATECH instituted a series of projects that included more of the supplier infrastructure including tool benchmarking projects, pad and slurry projects along with supporting University research at Rensselaer Polytechnic Institute. From 1988 and throughout the early 90’s, SEMATECH became the main source of information on CMP for a majority of US. companies. Spread of this technology outside the US. was first prompted by IBM's DRAM development alliance with Toshiba of Japan and Siemans of Germany. IBM established a research alliance at their East Fishkill site in 1990, and this gave Toshiba and Siemans a head-start on CMP technology. IBM’s prominence in semiconductor technology drove it’s research alliances and through it’s influence in the industry. CMP into the market through Two events then drove the acceleration of information on CMP into the mainstream. A series of downsizings at IBM from 1990 to 1994 left engineers and technicians with CMP experience in a situation with attractive severance packages and lucrative job offers from the blossoming CMP industry. At the same time, the first assignees in CMP at SEMATECH found themselves with a valuable skill and multiple job offers from young CMP suppliers hungry for CMP experience. With the migration of people, CMP technology was no longer a subject that could be contained. The importance of patents in CMP began to increase the as can be seen in Figure 1 which shows growth of patents filed in the US. [2] Importance of CMP in Semiconductor We As device dimensions shrink from 0.5 um and below, the trend has been towards polishing of more layers. In 1994, an average of three layers were polished. [3] Today, for a four level metal process, an average of 6—10 polishing steps are With the future pointing to six levels of metallization and Cu Metallization technology, this trend is expected to continue. Based upon the use of polishing today, a 5000 Wafer Start Per Week require 15-25 polishing tools assuming 60% tool utilization and a 20 wafer per Clearly, CMP tools will comprise a significant portion of a semiconductor fabrication plant. The support equipment needed to support CMP manufacturing is also significant. CMP tools must be supported by slurry distribution systems, CMP Post Clean systems, metrology tools and Recurring expense items such as slurry and CMP pads comprise a large portion used. Factory would hour tool. other equipment. of the semiconductor factory expense budget. 1998 Symposium on VLSI Technology Digest of Technical Papers 3 4 Growth of the Supplier Infrastructure Based upon IBM history, the original CMP supplier base consisted of Westech and Strasbaugh for tools, Cabot slurry (then distributed by Rippey Corp.) and Rodel for polishing pads. Westech was the tool of choice for most US. companies based upon the technology transfer from SEMATECH. Strasbaugh became the dominant tool in Asia. Improvements in throughput quickly became a key issue for CMP tools. Cybeq and SpeedFAM began offering multiheaded tools to address this issue. SpeedFAM was able to make significant advances in the US. market when it began working with SEMATECH. The promise of higher thoughput per square foot and the risk decrease that came from sharing tool development with other US companies though SEMATECH, gave many US companies the confidence to switch to SpeedFAM. Equipment productivity and reliability was a key issue for the more experienced CMP users. Intel with it’s significant lead in CMP technology was well aware of the importance of CMP and the vulnerability of it’s operations with respect to reliance upon the CMP tool supplier base. This lead to Intel developing it’s own CMP tool with a small supplier near Intel’s Portland Oregan facility. Gaard Automation was recruited to build a secret Intel CMP tool that addressed many of the issues with CMP technology of the time. Intel's tool had an extremely small footprint, high productivity, decreased slurry useage, and a motion that attempted to address the issue of within wafer uniformity. Intel’s “home grown” tool became the tool of record for metal CMP in Intel factories and accounted for a substantial percentage of the CMP tool installed base. The rights to this tool were later sold to IPEC (formerly Westech), and this tool today is marketed as the IPEC 676. In Japan. Toshiba began to develop a strong Japanese tool supplier by working with Ebara. Ebara paid careful attention to tool reliability and made the addition of a built in cleaner. Ebara also embarked upon a substantial development effort that dwarfed the efforts of other tool suppliers and most semiconductor manufacturers at the time. Today these early tool suppliers continue to enjoy substantial market share. 0-7803—4700-6/98/$10.00 © 1998 IEEE It is the significant growth of the overall CMP infrastructure that carries the weight of the importance of this technology. Figure 2 shows the growth of the supplier infrastructure between 1992 and 1997. [4] Figure 3 shows the growth of the CMP tool market and how it has continued to grow beyond it’s original forecasted growth. [5] CMP tools were a $516M dollar market in 1997 and predictions are that CMP tools will be more than a 1 Billion dollar market by the year 2000. These numbers explain why today there are approximately 20 CMP tool suppliers vying for market share. Significant advances have been made by slurry companies with approximately 20 Slurry companies now competing to provide slurry. The complexity of the interaction of the CMP pad with the process has meant slower growth for the pad market, but approximately 10 other companies are making inroads to this market. CMP Post-Clean, traditionally accomplished by brush scrubbers, has become a large market. Although dominated by OnTrak in the US and Dainippon Screen in Japan, approximately 17 other suppliers now provide CMP PostClean systems. Many CMP tool suppliers have followed Ebara’s lead and are implementing post-clean into the tool. Other businesses that have developed to support CMP include Endpointing Process Control with almost 10 suppliers. Slurry Distribution has become a key part of providing CMP and 8 major suppliers now compete in that market. Finally, a key supplier segment that is likely to be the largest growth segment over the next few years is the waste treatment supplier infrastructure with approximately 10 suppliers now competing. Current Limitations and Future Challenges CMP is generally acknowledged to be an immature technology compared with other semiconductor technology fields. Quality control and process reproducibility continue to drive the cost of the CMP process. At Intel for example, quality, availability and total cost issues associated with CMP consumables are estimated to be 2—7x that of other fab chemicals. [6] Future developments in CMP should focus .on improved quality and process reproducibility. The environmental impact of CMP has become an important consideration 1998 Symposium on VLSI Technology Digest of Technical Papers and much growth is expected in the area of consumable reduction and slurry recycling. Industry meetings on CMP environmental issues are drawing significant interest from the Industry. These limitations in understanding are likely to be met by an increase in the research in the science of CMP. As with the supplier infrastructure, the growth of university research on areas related to CMP has matched the growth of the supplier infrastructure. In conclusion, the Semiconductor Industry needs to continue to emphasize the importance of developing core competencies in science and engineering to support the development of the science of CMP. Key fields include polymer chemistry, particle metrology, synthesis and classification, reaction kinetics, colloid chemistry, surface chemistry and thermodynamics. Strong support of university research in these areas should be made to insure advances in the field and graduates ready to join the CMP industry. References [1] Mike Fury, “The early days of CMP” Solid State Technology, pp. 81-86, May 1997 [2] Tom Tucker, private communication [3] Mansour Moinpour, "Productivity Improvements in Chemical Mechanical Polishing: A User’s Perspective", NCCAVS User Group, 1997. [4] Tom Tucker, private communication [5] Mike Martinez, private communication [6] Ara Philipossian, private communication Acknowledgments The author would like to thank many industry colleagues and friends who contributed to the ideas in this paper. Special thanks to Mike Fury of Allied Signal, Mike Martinez of OnTrak. Rahul Jairath of Lam Research, Tom Tucker of Laredo Technology and Ara Philliposiun of Intel. Figure 1. Mm of CMP Plhnh filed Number of Suppllen 15 I0 PM Mology Ckln Slulfy m_ Ema Figure 3. WM. CMP Foth MU"! W ,§§§§§§§§§ 1998 Symposium on VLSI Technology Digest of Technical Papers ...
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H-CMP-history - 1 2 1(Invited Chemical Mechanical Polishing The Impact of a New Technology on an Industry Kathleen A Perry Obsidian Inc 47485

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