PLD's - PLDs Password_ Copyright 2009 Daniel Tylavsky PLDs...

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PLD’s Password_________________ © Copyright 2009 Daniel Tylavsky
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There is a need to implement combinational logic functions using a minimum amount of hardware. We’re going to look at three ways of doing this: Multiplexers Decoders Programmable Logic Devices Programmable Array Logic (PAL) PROM Programmable Logic Array (PLA) PLD’s
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EX: Assuming you have all variables and their complements available, implement the following function using 8-1, 4-1, and 2-1 multiplexers. A B C G 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 I0 8-1 I1 Mux I2 I3 I4 Y I5 I6 I7 S2 S1 S0 A B C 0 1 0 1 1 1 0 0 G PLD’s
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G A B A B C G 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 I0 4-1 I1 Mux I2 I3 Y S1 S0 C C C 1 0 B C G I0 4-1 I1 Mux I2 I3 Y S1 S0 A 1 0 TEAMS: Complete the implementation for the 4-1 Mux at left. I0 4-1 I1 Mux I2 I3 Y S1 S0 G A C A PLD’s
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A B C G 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 I0 2-1 I1 Mux Y S G A C B Implementing a 3 variable function with a 2-1 mux is not always possible. Implementation requires that the function can be expressed in the form:
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This note was uploaded on 10/21/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.

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PLD's - PLDs Password_ Copyright 2009 Daniel Tylavsky PLDs...

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