Building a PROM

Building a PROM - Building a PROM Based Controller Using...

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Building a PROM Based Controller Using LogicWorks Password_____None ________ © Copyright 2008 Daniel Tylavsky
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Mealy Finite State Machine 0 0 REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR +5 V Reset Clock Data Bus Synchronizing Instruction Register State Register Bit 02: Load IR In5 In4 In3 In2 In1 In0 Out15 Out14 Out13 Out12 Out11 Out10 Out09 Out08 Out07 Out06 Out05 Out04 Out03 Out02 Out01 Out00 Inst. Decoder PROM Bit 01: Next State Bit 1 Bit 00: Next State Bit 0 Bit 06: Load ACC Bit 15: X Bit 14: X Bit 12: X Bit 13: X Bit 11: Logic/~Arith Bit 10: /~Invert Bit 09: /~A_Only Bit 08: Use PC Bit 07: Load MAR Bit 05: ACC to Data Bus Bit 04: Read Bit 03: Write IR3 IR2 IR1 IR0 SR1 SR0 ID3 ID2 ID1 ID0 ID7 ID6 ID5 ID4 ID11 ID10 ID9 ID8 ID15 ID14 ID13 ID12 A3 A2 A1 A0 ID1 ID0 Our synchronized Mealy machine controller has the following block-diagram form: External Input { 2 State Variables Fedback Control Outputs Functions Synchronized Input Building a LogicWorks PROM
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We argued that these are the controller outputs and the PROM contents, where the address in memory is (Opcode, Pres.State). We must enter this information in order into our controller PROM. Load ACC Add to ACC Stop 0 1 0 00 01 02 03 00 01 02 03 00 01 02 03 Description Pin Number Next State Bit 1-0 01 00 00 00 01 00 00 00 01 01 00 00 Load IR 2 1 0 0 0 1 0 0 0 1 0 0 0 Write
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This note was uploaded on 10/21/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.

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Building a PROM - Building a PROM Based Controller Using...

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