Controller Design

Controller Design - Controller Design Password_None...

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Controller Design Password_____None ________ © Copyright 2009 Daniel Tylavsky
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To complete our microprocessor we will need to add two major circuits: Address Generation Circuit Controller Let’s look at the address generation circuit first. To understand why the circuit is designed the way it is, we need to know how we will store instructions in memory. Controller Design
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Addr Memory Q Opcode Q+1 Opcode Q+2 Data Q+3 Opcode Q+4 Data Q+5 Data Instruction w/o Data Instruction w/ Data Instruction w/ 2 Pieces of Data We will store instructions and data in our simulated ROM as: Controller Design
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Addr Memory Q Load Acc Q+1 3 Q+2 Add Q+3 5 Q+4 Store to Addr Q+5 E Q+6 Load Acc Q+7 3 Q+8 Negate Q+9 C A program portion in memory might look like: } Load the accumulator with ‘3’. Our ROM-based controller will have the capability of implementing each of these instructions. } Add ‘5’ to the accumulator. } Store results from ACC to memory location ‘E’. } Etc. Controller Design
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Our instruction layout shows that instructions (with data), which are to be executed sequentially, are laid out in consecutive locations memory. We will need circuitry that can both: access memory locations sequentially, and, access a memory location out of order (e.g. “Store to location E”). Controller Design
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0 0 REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR INC_4 A2 A3 Y3 INC Y2 Y1 Y0 A0 A1 CRY +5 V Reset Clock Data Bus Load MAR (Load Memory Address Register) Use PC (Use PC for Address) Memory Address Register Program Counter Register Address Bus PC MAR Program Counter PC3 PC2 PC1 PC0 PC3 PC2 PC1 PC0 PC3 PC2 PC1 PC0 A3 A2 A1 A0 MR3 MR2 MR1 MR0 PC (Program Counter Bus) MUX_4 A2 A3 Y3 Y2 Y1 Y0 A0 A1 A/~B B2 B3 B0 B1 This program counter and address generation circuit can do this. 0 1 1 0 0 0 1 1 1 2 2 2 2 3 Let’s first look at how the PC operates to access locations sequentially. Controller Design
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0 REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR INC_4 A2 A3 Y3 INC Y2 Y1 Y0 A0 A1 CRY +5 V Reset Clock Data Bus Load MAR (Load Memory Address Register) Use PC (Use PC for Address) Memory Address Register Program Counter Register Address Bus PC MAR Program Counter PC3 PC2 PC1 PC0 PC3 PC2 PC1 PC0 PC3 PC2 PC1 PC0 A3 A2 A1 A0 MR3 MR2 MR1 MR0 PC (Program Counter Bus) MUX_4 A2 A3 Y3 Y2 A0 A1 Let’s look at how the PC can drive the address bus with a non-sequential address. 2 2 2 3 E E E Now let’s place the PC in the partially completed design. Controller Design
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DB Logic/~Arith /~Invert /~A_Only Load ACC BUFFER_4 A2 A3 Y3 EN1 Y2 Y1 Y0 A0 A1 EN2 0 (Accumulator) REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 A3 A2 A1 A0 Gnd 0 A3 A2 A1 A0 A3 A2 A1 A0 0 REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR REG A2 A3 Y3 EN Y2 Y1 Y0 A0 A1 CLK CLEAR A3 A2 A1 A0 A3 A2 A1 A0 Clock 0 BUFFER_4 A2 A3 Y3 EN1 Y2 Y1 Y0 A0 A1 EN2 A3 A2 A1 A0 BUFFER_4 A2 A3 Y3 EN1 Y2 Y1 Y0 A0 A1 EN2 AD00 A3 A2 A1 A0 BUFFER_4 A2 A3 Y3 EN1 Y2 Y1 Y0 A0 A1 EN2 AD01 A3 A2 A1 A0
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This note was uploaded on 10/21/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.

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Controller Design - Controller Design Password_None...

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