Memory Systems

Memory Systems - Memory Systems Password_ Copyright 2009...

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Memory Systems Password_________________ © Copyright 2009 Daniel Tylavsky
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Last time we designed a memory cell. OE Out WE D IN Q WE OE Q + Out 0 0 D IN D 0 1 D Z 1 0 Q Q 1 1 Q Z Read Write Store Not Used Memory Systems
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Let’s design a 4 (words) X 1 (bit) RAM 2-4 Y0 Decoder Y1 ENB Y2 Y3 S1 S0 Cell 0 Cell 1 Cell 2 Cell 3 A1 A0 CS D I WE O E Memory Systems
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Open “4x1ram.cct” and verify the performance of the memory circuit. The memory feedback path is modified to account for the limitations of LogicWorks™. Memory Systems Cell 3 Cell 2 Cell 1 Cell 0 1 0 1 0 1 1 0 1 1 Data Out Q0 Q1 Q2 Q3 S0 S1 EN 0 1 2 3 4 5 6 7 8 9 A B C D E F Data In CS' OE' WE' WE'
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2-4 Y0 Decoder Y1 ENB Y2 Y3 S1 S0 Cell 0 Cell 1 Cell 2 Cell 3 A1 A0 CS D I WE O E Assigning blocks to each circuit subgroup Read0 Read1 Read3 Read2 Read/ Write Logic Write0 Write1 Write3 Write2 . 4X1 Memory Cell Array Memory Systems
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Now let’s design a 4X4 RAM Read Write I 0 D 0 4X1 Cell I 1 D 1 4X1 Cell I 2 D 2 4X1 Cell I 3 D 3 4X1 Cell 2-4 Y0 Decoder Y1 ENB Y2 Y3 S1 S0 A1 A0 CS Read/ Write Logic OE WE Memory Systems
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This note was uploaded on 10/21/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.

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Memory Systems - Memory Systems Password_ Copyright 2009...

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