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Unformatted text preview: 2009 2009 Edition © by D. G. Meyer Introduction to Digital System Design Module 1 Static and Dynamic Behavior of Digital Circuits Module Module 1
Desired Desired Outcome: “An ability to analyze static and dynamic behavior of digital circuits” – Part A: Review of Basic Electronic Components – Part B: Logic Signals and Gates – Part C: Steady State Electrical Behavior of CMOS Circuits – Part D: Dynamic Behavior of CMOS Circuits – Part E: Other CMOS Input/Output Structures and Logic Families 2009 2009 Edition © by D. G. Meyer Introduction to Digital System Design Module 1A Review of Basic Electronic Components Basic Basic Electronic Concepts
VOLTAGE VOLTAGE – difference in electrical potential, expressed in volts CURRENT CURRENT – the flow of charge in a conductor between two points having a difference in potential, potential, expressed in amperes (amps) amperes Waterfall Waterfall analogy – voltage is proportional to height height of waterfall, current is proportional to current flow flow of waterfall POWER POWER – amount of energy, expressed in watts watts, typically calculated as the product of the voltage drop across a device and the voltage current current flowing through it Basic Basic Electronic Concepts
RESISTOR RESISTOR – a device that limits the amount of current flowing through a circuit, measured in ohms (Ω) ohms Resistance Resistance is also referred to as impedance impedance The The inverse of impedance is conductance conductance Fundamental Fundamental relationship – the voltage drop (VR) across a resistor is equal to the product of the current flowing through it (IR) and the value of the Ohm’s resistance (R) ⇒ called Ohm’s Law VR = IR x R Basic Basic Electronic Concepts
CAPACITOR CAPACITOR – a device that stores an electric farads charge, measured in farads (F) Fundamental Fundamental relationships – a resistorcapacitor (RC) network charges resistorand and discharges exponentially – the voltage across a capacitor cannot change instantaneously – the product of R and C is called the RC RC time constant VC = VIN x (1  et/RC) VIN VC Basic Electronic Concepts
DIODE DIODE – a device that restricts the flow of anode current to a single direction (from its anode to its cathode) cathode Fundamental Fundamental relationships – a diode through which current is flowing (because the voltage at the anode is greater forward than at the cathode) is forward biased – if current is not flowing through a diode (because the voltage at the cathode is greater than at the anode), the diode is reverse reverse biased Basic Electronic Concepts
LIGHT LIGHT EMITTING DIODE (LED) – a diode that emits visible (red/yellow/green/blue/white) or invisible (infrared) light when forwarded biased Fundamental Fundamental relationships – the brightness of an LED is proportional to the amount of current flowing through it forward (called the forward current) – a resistor is placed in series with an LED to resistor limit the amount of current flowing through it – the voltage drop across an LED when it is forward biased is called the forward voltage forward Basic Basic Electronic Concepts
FIELD FIELD EFFECT TRANSISTOR (FET) – a 3terminal device (gate, source, drain) that 3provides a voltagecontrolled impedance voltageTwo Two basic types – Nchannel: high potential on gate causes high transistor transistor to turn on (low impedance between source and drain) – Pchannel: low potential on gate causes low transistor to turn on
Nchannel D Pchannel D G S G S Basic Basic Electronic Concepts
FET FET acts as a voltagecontrolled switch voltage
VCC Nchannel G +
VG
S RL D S Voltagecontrolled resistance: increase VGS → decrease RDS Note: normally, VGS ≥ 0 As RDS decreases, power delivered to load (RL) increases  FETs are used to construct Complementary Metal Oxide Semiconductor (CMOS) logic circuits and can also be used to switch DC loads Basic Basic Electronic Concepts
BIPOLAR BIPOLAR JUNCTION TRANSISTOR (BJT) – a 3terminal device (base, emitter, collector) 3that provides a currentcontrolled impedance currentTwo Two basic types – Nchannel: small current flowing into base small through through emitter causes large current to flow large from collector to emitter – Pchannel: small current flowing out of base small through emitter causes large current to flow large from emitter to collector
Nchannel C E Pchannel C E B B Basic Basic Electronic Concepts
BJT BJT acts like a currentcontrolled switch current NPN
small B→E current B C E LARGE C→ E CURRENT BJTs are used to construct TransistorTransistor Logic (TTL) and can also be used to switch high voltage/current DC loads Basic Basic Electronic Concepts
INTEGRATED INTEGRATED CIRCUIT (IC) – a collection of logic gates and/or other electronic circuits fabricated on a single silicon chip PROGRAMMABLE PROGRAMMABLE LOGIC DEVICE (PLD) – an integrated circuit onto which a generic logic logic circuit can be programmed (and be subsequently erased and reprogrammed) reCOMPUTER COMPUTER – a digital device that sequentially executes a stored program MICROPROCESSOR MICROPROCESSOR – a singlechip singleembodiment of the major functional blocks of a computer Basic Electronic Concepts
MICROCONTROLLER MICROCONTROLLER – a complete computer on a chip, including integrated peripherals (memory, analogtodigital analogtoconversion, serial communications, pulsepulsewidth modulation, timers, network interface) SOCIALLY SOCIALLY REDEEMING – something that has inherent value (like studying digital systems design) DIGIJOCK(ETTE) DIGIJOCK(ETTE) – a person who enjoys learning about digital systems 2009 2009 Edition © by D. G. Meyer Introduction to Digital System Design Module 1B Logic Signals and Gates Reading Reading Assignment: 3rd Ed., pp. 7995; 4th Ed., pp. 7996 7979Instructional Objectives:
To To learn a definition of Boolean algebra To To learn about the three major operators in Boolean Boolean algebra and the symbols used to represent represent them To To learn about the basic logic gates that are used to implement digital circuits To To learn about the circuits that are used to implement logic gates Outline Outline
Definition Definition of Boolean Algebra Logic Logic signals and assertion levels Combinational Combinational digital logic circuits Boolean’s Boolean’s “big three” operators Logic Logic families CMOS CMOS logic Switch Switch analogies and implementations Boolean Boolean Algebra
Definition Definition: A Boolean Algebra is a is triplet [K, +, •] consisting of a finite set of elements, K, subject to an equivalence relationship, “=”, and two binary binary operators denoted “+” (OR) and “•” (AND); such that for every element X and Y contained in K, the operations X + Y and X • Y are uniquely defined and Huntington’s Postulates Huntington’s (described later) are satisfied. Boolean Boolean Algebra
Definition An equivalence Definition: An equivalence relation is
some relation R defined on a set K which satisfies the following three basic properties: – Reflexive  for every X in the set K, the relationship relationship XRX holds – Symmetric  for every X and Y in the set K, the relationship YRX holds whenever the relationship XRY holds – Transitive  for every X, Y, and Z in the set K, if the relationships XRY and YRZ hold, then the relationship XRZ holds Boolean Boolean Algebra
Definition Definition: A binary variable, X, is a twobinary twovalued quantity such that: – if X ≠ 1, then X = 0 – if X ≠ 0, then X = 1 K = {0, 1} {0, Boolean Boolean Algebra
Huntington’s Huntington’s Postulates
P1. The operations are closed For all X and Y ∈ K, (a) X + Y ∈ K (b) X • Y ∈ K P2. For each operation, there exists an identity element (a) There exists an element 0 ∈ K such that for all X ∈ K, X + 0 = X (b) There exists an element 1 ∈ K such that for all X ∈ K, X • 1 = X Boolean Boolean Algebra
Huntington’s Huntington’s Postulates
P3. The operations are commutative For all X and Y ∈ K, (a) X + Y = Y + X (b) X • Y = Y • X P4. The operations are distributive For all X, Y and Z ∈ K, (a) X + (Y • Z) = (X + Y) • (X + Z) (b) X • (Y + Z) = X•Y + X•Z Boolean Boolean Algebra
Huntington’s Huntington’s Postulates
P5. For every element X ∈ K there exists an element X´ ∈ K (called the complement X´ complement of X) such that (a) X + X´ = 1 (b) X • X´ = 0 X´ P6. There exist at least two elements, X and Y ∈ K, such that X ≠ Y Logic Logic Signals
A logic value, 0 or 1, is often referred logic bi digit bit to as a binary digit or bit The The words “LOW” and “HIGH” are often used in place of “0” and “1” to refer logic refer to logic signals
– LOW  a signal in the range of “lower” voltages (e.g., 0  1.5 volts for CMOS logic), which is interpreted as a logic 0 – HIGH  a signal in the range of “higher” voltages (e.g., 3.5  5.0 volts for CMOS 3.5 logic), which is interpreted as a logic 1 Logic Logic Signals
Note Note: The assignment of 0 and 1 to LOW assignment LOW and HIGH, respectively, is referred to as HIGH a positive logic convention (or simply positive (or “positive logic”) – a positive logic signal that is asserted asserted is in the HIGH state, and is therefore HIGH referred to as an “active high” signal “active signal – a positive logic signal that is negated negated is in the LOW state LOW Logic Logic Signals
The opposite The opposite assignment (1 to LOW and LOW 0 to HIGH) is referred to as a negative to HIGH negative logic convention (or “negative logic”) (or – a negative logic signal that is asserted asserted is is in the LOW state, and is therefore LOW referred referred to as an “active low” signal “active signal – a negative logic signal that is negated negated is in the HIGH state HIGH Logic Logic Signals
A logic circuit can be represented as simply logic a “black box” with a certain number of inputs and outputs
X1 X2 . . . f f (X1,X2, … , Xn) Xn Xn Since Since the inputs of a digital logic circuit can be viewed as discrete 0 and 1 values, the circuit’s “logical” operation can be described using a table that lists discrete 0 functional and 1 functional outputs Combinational Combinational Circuits
A logic circuit whose outputs depend only logic on its current inputs is called a combinational circuit A truth table can be used to fully describe truth the operation of a combinational logic circuit circuit Three Three basic logic functions – AND, OR, and NOT – can be used to build any digital any logical combinational logic circuit (idea of logical completeness) Boolean’s Boolean’s Big Three
An AND An AND gate produces a 1 output if and only if all of its inputs are 1 An OR An OR gate produces a 1 output if one or more of its inputs are 1 A NOT gate (usually called an inverter) NOT inverter produces produces an output value that is the inversion opposite of its input value bubble Another Another “102” (Two)
A NAND gate produces the opposite of an NAND opposite AND AND gate’s output A NOR gate produces the opposite of an NOR opposite OR gate’s output OR Time Time Matters
Logic Logic gates require a certain amount of “think time” to produce a new output in response to changing inputs – referred to as the propagation delay of the gate propagation The The propagation delay of a logic circuit may vary vary depending on whether its output signal signal is transitioning from lowtohigh (rise lowtopropagation delay) or from hightolow (fall hightopropagation delay) A timing diagram can be used to show how timing a logic circuit responds to timevarying timeinput signals Time Time Matters
Time Time response of a combinational circuit Logic Logic Families
There There are many ways to design a digital logic many gate, from mechanical relays and vacuum tubes to microscopic transistors The The most successful bipolar logic family is bipolar TransistorTransistor Logic (TTL) ransistorComplementary MetalOxide Semiconductor etal(CMOS) circuits now account for the vast majority of the worldwide Integrated Circuit (IC) market CMOS CMOS logic is both the most capable and the easiest to understand commercial digital logic technology CMOS Logic
CMOS logic levels indeterminate region undefined input yields undefined output Note: CMOS circuits using other power supply voltages (e.g., 3.3 or 2.7 volts) partition the voltage range similarly CMOS Logic
MOS transistor – Modeled as a 3terminal device that acts like a voltagecontrolled resistance In digital logic applications, a MOS transistor is operated so that its resistance is either very high (transistor is “off”) or very low (transistor is “on”) CMOS Logic
There are two types of MOS transistors – Nchannel MOS (NMOS) D G
VG
S Voltagecontrolled resistance: increase VGS → decrease RDS Note: normally, VGS ≥ 0 S S
Voltagecontrolled resistance: decrease VGS → decrease RDS Note: normally, VGS ≤ 0 – Pchannel MOS (PMOS)
VG
S G D Basic CMOS Inverter Circuit
circuit diagram logical behavior switch analogy Basic CMOS NAND Gate
“OR” “AND” Basic CMOS NOR Gate
“AND” “OR” Exercise:
Transform this 2input NOR gate into a 3input NOR gate Exercise:
Transform this 2input NOR gate into a 3input NOR gate Exercise:
Transform this 2input NOR gate into a 3input NOR gate C 2009 2009 Edition © by D. G. Meyer Introduction to Digital System Design Module 1C Steady State Electrical Behavior of CMOS Circuits Reading Reading Assignment: 3rd Ed., pp. 96113; 4th Ed., pp. 96114 9696Instructional Objectives:
To To be able to read and understand device data sheets and specifications, in order to create reliable and robust realworld circuits realand and systems To To be able to use data on logic levels to calculate the DC noise margin of a circuit To To be able to use data on sourcing and sinking currents to calculate fanout fanTo To learn about the deleterious side effects of excessive output loading, unused inputs, noise spikes, and electrostatic discharge Outline Outline
Overview Overview Data Data sheets Noise Noise Logic Logic levels and noise margins Sourcing Sourcing and sinking current NonNonideal inputs FanFanin and Fanout FanEffects Effects of loading Unused Unused inputs Current Current spikes and decoupling Electrostatic Electrostatic discharge Overview Overview
Objective: Objective: To be able to design real circuits real using CMOS or other logic families – need to ensure that the “digital abstraction” is valid for a given circuit – need to provide adequate engineering design margins to ensure that a circuit will work properly under a variety of conditions – need to be able to read and understand data sheets and specifications, in order to create reliable and robust realworld realcircuits and systems Data Sheet for a Typical CMOS Device Noise Noise
The The main reason for providing engineering design margins is to ensure proper operation in the presence of noise Examples Examples of noise sources: – cosmic rays – magnetic fields generated by machinery – power supply disturbances – the “switching action” of the logic circuits themselves Logic Logic Levels and Noise Margins
Typical inputTypical inputoutput transfer characteristic of a CMOS inverter Problem: Typical, NOT guaranteed! Logic Logic Levels and Noise Margins
Factors Factors that cause the transfer characteristic to vary
– power supply voltage – temperature – output loading – conditions under which a device was fabricated Sound Sound engineering practice dictates that we use more “conservative” specifications for LOW and HIGH Logic Logic Levels and Noise Margins
Definitions Definitions: – VOHmin  the minimum output voltage in output
HIGH the HIGH state –VIHmin  the minimum iinput voltage nput
guaranteed guaranteed to be recognized as a HIGH HIGH –VILmax  the maximum iinput voltage nput
guaranteed to be recognized as a LOW LOW –VOLmax  the maximum output voltage in output
the LOW state LOW Logic Levels and Noise Margins
CMOS levels are typically a function of the power supply rails” – VOHmin Vcc – 0.1v – VIHmin 70% of Vcc – VILmax 30% of Vcc – VOLmax GND + 0.1v
DC noise margin is a measure of how much noise it takes to corrupt a worstcase output voltage into a value that may not be recognized properly by an input Data Sheet for a Typical CMOS Device Logic Logic Levels and Noise Margins
Calculation Calculation of DC noise margin (or the “noise immunity margin”) DCNM = min (VOHmin – VIHmin, min VILmax – VOLmax) Example HCExample: HCseries CMOS DCNM = min (4.4 – 3.15, 1.35 – 0.1) min
= 1.25 v Sourcing Sourcing and Sinking Current
CMOS CMOS gate inputs have a very high impedance and consume very little current from the circuits that drive them – I IL the maximum current that flows into current the input in the input in the LOW state LOW the maximum current that flows into current the input in the HIGH state input HIGH – I IH For CMOS logic, the input current is very small – it takes very little power to maintain a CMOS input in either the HIGH or LOW state Sourcing Sourcing and Sinking Current
Often Often times gate outputs need to drive devices that require a nontrivial amount of noncurrent to operate – called a resistive load resistive load or D.C. load D.C. load When When driving a resistive load, the output of a CMOS circuit is not nearly as ideal as CMOS described described previously In In either output state, the CMOS output transistor that is “on” has a nonzero nonresistance, and a load connected to its output terminal will cause a voltage drop across this resistance Sourcing Sourcing and Sinking Current
IC IC manufacturers specify a maximum load for the output in each state (HIGH or LOW) and guarantee a worstcase output voltage worstfor that load – IOLmax  the maximum current that the current
output output can “sink” in the LOW state while LOW still maintaining an output voltage no no greater than VOLmax – IOHmax  the maximum current that the current
output can output can “source” in the HIGH state HIGH while still maintaining an output voltage no no less than VOHmin Sourcing and Sinking Current
Circuit definitions of IOLmax and IOHmax X X sinking current (positive)
current arrow
NOTE: Convention is for the input/output current arrows to point “in” sourcing current (negative) Sourcing Sourcing and Sinking Current
Most Most CMOS devices have two sets of loading specifications – “CMOS loads” – device output connected to other CMOS inputs, which consume very little current – “D.C. loads” – device output connected to resistive loads (devices that consume significant current) Note: With “D.C. loads” the output voltage swing of a CMOS circuit may significantly degrade NonNonideal Inputs
If If the inputs to a CMOS circuit are not close to the Vcc / GND rails, the “on” transistor may not be fully on and the “off” transistor fully may not be fully off – causing power fully dissipation of the device to increase FanFanin
Definition Definition: The number of inputs a gate can have in a particular logic family is called the logic family’s fanin fanCMOS CMOS gates with more than two inputs can be obtained by extending the “series“seriesparallel” parallel” circuit designs (e.g., for NAND and NOR NOR gates) illustrated in the previous lecture In In practice, the additive “on” resistance of series transistors limits the fanin of CMOS fangates to a relatively small number Gates Gates with a large number of inputs can be made faster and smaller by cascading gates with fewer inputs FanFanout
Definition Definition: The number of gate inputs that a gate output can drive without exceeding without its worstcase loading specifications worst– depends on characteristics of both the output device and the inputs being driven – must be examined for both the “sourcing” and “sinking” cases – practical limitations due to capacitive loading (AC vs. DC fanout) fan FanFanout = min ( IOHmax / IIH, IOLmax / IIL) min Data Sheet for a Typical CMOS Device FanFanout
Example HCExample: HCseries CMOS FanFanout = min ( IOHmax / IIH, IOLmax / IIL ) min = min (0.02 mA / 0.001 mA, 0.02 mA / 0.001 mA) min
= 20
Note: DC fanout is considerably greater in this case if the output voltage swing is degraded … but DCNM is lower and signal transitions times are longer, causing speed degradation Practical FanPractical Fanout
In In a practical application, a gate output may drive a “mixture” of loads HIGHHIGHstate fanout – The sum of the IIHmax fanvalues of all the driven inputs must be less less than than or equal to the IOHmax of the driving output output LOWLOWstate fanout – The sum of the IILmax fanvalues of all the driven inputs must be less less than or equal to the IOLmax of the driving output The “practical” fanout is the minimum of the HIGH and LOWstate fanouts Clicker Quiz 1. For CMOS gates, VIHmin is typically:
A. B. C. D. E. 10% of the supply voltage (Vcc) 30% of the supply voltage (Vcc) 50% of the supply voltage (Vcc) 70% of the supply voltage (Vcc) 90% of the supply voltage (Vcc) 2. For CMOS gates, the switching threshold
is typically: A. B. C. D. E. 10% of the supply voltage (Vcc) 30% of the supply voltage (Vcc) 50% of the supply voltage (Vcc) 70% of the supply voltage (Vcc) 90% of the supply voltage (Vcc) 3. If a CMOS gate input voltage is 50% of its Vcc
(power supply) voltage, then: A. the logic gate will dissipate less power than it would if if the input was 1% of its power supply voltage B. the logic gate will dissipate less power than it would if the input was 99% of its power supply voltage C. the logic gate will dissipate more power than it would if the input was either 1% or 99% of its power supply voltage D. the logic gate will dissipate no power E. none of the above DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH – VOL)/2 VOH = 3.50 V IOH = −5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 µA IIL = −2.0 mA 4. 4. The DC noise margin for this logic family is:
A. B. C. D. E. 0.50 V 1.00 V 1.50 V 2.00 V none of the above DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH – VOL)/2 VOH = 3.50 V IOH = −5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 µA IIL = −2.0 mA 5. 5. The practical fanout for this logic family is:
A. B. C. D. E. 1 2 5 10 none of the above Effects Effects of Loading
Loading Loading a gate output beyond its rated fanout can have several deleterious effects: fan– in the LOW state, the output voltage (VOL) may increase beyond VOLmax – in the HIGH state, the output voltage (VOH) may fall below VOHmin – output rise and fall times may increase beyond their specifications – the operating temperature of the device reducing may increase, thereby reducing the reliability reliability of the device and eventually failure causing device failure Unused Unused Inputs
Unused Unused (“spare”) CMOS inputs should never never be left unconnected (“floating”) (“floating”) A small amount of circuit noise can small temporarily make a floating input look HIGH Instead, Instead, unused inputs should be: – tied to another input of the same gate – tied HIGH (for AND and NAND gates) – tied LOW (for OR and NOR gates)
pullup resistor pulldown resistor Current Current Spikes and Decoupling
When When a CMOS gate output changes state, the P and Nchannel transistors are both PNpartially on simultaneously, causing a current current spike Current Current spikes often show up as noise on noise the the power supply and ground connections Decoupling Decoupling capacitors (between Vcc and GND) must be distributed throughout a printed circuit board (PCB) to supply extra current during transitions to CMOS ICs VERY IMPORTANT FOR SENIOR DESIGN PROJECTS!! Electrostatic Electrostatic Discharge
CMOS CMOS device inputs are subject to damage from electrostatic discharge (ESD) Apply Apply these precautions in lab: – before handling a CMOS device, touch a source source of earth ground earth – transport CMOS devices in conductive conductive bags, bags, foam, or tubes – handle circuit boards containing CMOS devices by the edges; touch a ground edges terminal on the board to earth ground before “poking around with it” Clicker Quiz 1. The nominal (minimum) case for the outputs
of logic family “A” to be able to successfully drive the inputs of logic family “B” is: A. fanoutA→B ≤ 1 and DCNMA→B < 0 B. fanoutA→B ≤ 0 and DCNMA→B < 1 C. fanoutA→B ≥ 1 and DCNMA→B > 0 D. fanoutA→B ≥ 0 and DCNMA→B > 1 E. none of the above 2. When a gate’s rated IOH specification is
exceeded, the following is likely to happen: A. the VOH of the gate will increase and the tTLH of the gate will decrease B. B. the VOH of the gate will decrease and the tTLH of the gate will increase C. the VOL of the gate will increase and the tTHL of the gate will increase D. the VOL of the gate will decrease and the tTHL of the gate will decrease E. none of the above 3. When a gate’s rated IOL specification is
exceeded, the following is likely to happen: A. the VOH of the gate will increase and the tTLH of the gate will decrease B. B. the VOH of the gate will decrease and the tTLH of the gate will increase C. the VOL of the gate will increase and the tTHL of the gate will increase D. the VOL of the gate will decrease and the tTHL of the gate will decrease E. none of the above 4. The largest source of noise in a digital
circuit is from: A. RF communication devices (e.g., cell phones) B. B. cosmic rays C. power line disturbances D. the logic gates themselves E. none of the above 5. Electromagnetic interference could cause
a “floating” (unconnected) gate input to: A. change from hightolow or from lowtohigh B. B. increase the VIH of the gate relative to its specified value C. decrease the VIL of the gate relative to its specified value D. pick up the satellite broadcast of a Purdue basketball victory E. none of the above 2009 2009 Edition © by D. G. Meyer Introduction to Digital System Design Module 1D Dynamic Behavior of CMOS Circuits Reading Reading Assignment: 3rd Ed., pp. 113122; 4th Ed., 114128 113114Instructional Objectives:
To To learn what factors influence the performance of a CMOS circuit To To learn the definition of transition time and how how to measure it To To learn how to analyze and estimate the transition times of a CMOS circuit To To learn about the effects of capacitive loading on a CMOS circuit To To learn the definition of propagation delay and how to measure it To To learn about the sources of power dissipation in a CMOS circuit Outline Outline
Overview Overview Transition Transition time Capacitive Capacitive loading Propagation Propagation delay Power Power consumption Overview Overview
The speed The speed and power consumption of a power CMOS device depend on the dynamic (“A.C.”) characteristics of the device and its load Logic Logic designers must carefully examine the effects of output loading and redesign where the the loading is too high Speed Speed (performance) depends on two characteristics: – transition time – propagation delay Transition Transition Time
Definition Definition: The amount of time that the output of a logic circuit takes to change from one state to another – rise time (tr or tTLH): the time an output time signal signal takes to transition from lowtohigh transition from low – fall time (tf or tTHL): the time an output time transition high tosignal takes to transition from hightolow Gate Gate outputs can not change state not instantaneously (i.e., instantaneously (i.e., with a transition time of zero) because they need to charge the stray charge capacitance of the wires and other components they drive Transition Time
“ideal” “less ideal” “reality” Note: tf is typically not equal to tr not Transition Transition Time
To To avoid difficulties in defining the endpoints, transition times are normally measured one of two different ways: – at the boundaries of the valid logic levels (i.e., VIHmin and VILmax) – at the 10% and 90% points of the output waveform Using Using the first convention (above), the rise and fall times indicate how long it takes for an output signal to pass through the (undefined) indeterminate region between indeterminate LOW LOW and HIGH HIGH Transition Transition Time
The The transition times of a CMOS circuit depend mainly on two factors: – the “on” transistor resistance – the load capacitance Stray Stray capacitance (called an “A.C. load”) (called arises from at least three different sources: – output circuits – including transistors, internal wiring, and packaging – wiring that connects a gate output to other gate inputs – input circuits – including transistors, internal wiring, and packaging Transition Transition Time
A gate output’s load can be modeled by an gate equivalent load circuit with 3 components: – RL and VL represent the D.C. load – they D.C. determine the steady state voltages and currents currents present and do not have much effect effect on transition times – CL represents the A.C. (capacitive) load – A.C. it determines the voltages and currents present while the output is changing, as well as how long it takes to change from one state to another Equivalent Equivalent Circuit for Transition Time Analysis of a CMOS Output Model Model of a CMOS LOWtoHIGH LOWtoTransition (with Negligible DC Load)
Capacitor is initially discharged RP CL rise time The time constant is RPCL VIHmin VILmax Model Model of a CMOS HIGHtoLOW HIGHtoTransition (with Negligible DC Load)
Capacitor is initially charged CL RN Fall time The time constant is RNCL VIHmin VILmax Example Example
Given Given that a CMOS inverter’s Pchannel MOSFET Phas an ON resistance of 200Ω, that its Nchannel NMOSFET has an ON resistance of 100Ω, and that the capacitive (or “A.C.”) load CL = 200 pF, calculate the fall time initial conditions Example Example
Given Given that a CMOS inverter’s Pchannel MOSFET Phas an ON resistance of 200Ω, that its Nchannel NMOSFET has an ON resistance of 100Ω, and that the capacitive (or “A.C.”) load CL = 200 pF, calculate the fall time initial conditions output goes low Example Example
Fall time calculation:
t = –Rn∗CL∗ln (Vout/VDD) = –100∗200∗10–12∗ln (Vout / 5.0) = –20∗109∗ln (Vout / 5.0) t3.5 = –20∗109∗ln (3.5/5.0) = 7.13 ns t1.5 = –20∗109∗ln (1.5/5.0) = 24.08 ns fall time = 24.08 – 7.13 = 16.95 ns Transition Transition Time
Conclusion Conclusion: An increase in load capacitance causes an increase in the RC time constant and a corresponding increase in the output transition (rise/fall) times Load Load capacitance must be minimized to minimized obtain obtain high circuit performance – this can be achieved achieved by: – minimizing the number of inputs driven by a given signal – creating multiple copies of the signal (using “buffers”) – careful physical layout of the circuit physical Transition Transition Time
Rule Rule of Thumb: In practical circuits, the transition time can be estimated using the estimated RC time constant of the charging or discharging circuit Final Final note: Calculated transition times are sensitive to sensitive to the choice of logic levels (i.e., VIHmin and VILmax) Example Example
Given Given that a CMOS inverter’s Pchannel MOSFET Phas an ON resistance of 200Ω, that its Nchannel NMOSFET has an ON resistance of 100Ω, and that the capacitive (or “A.C.”) load CL = 200 pF, estimate the estimate fall time and rise time and Fall time estimate: RN X CL = 100 X 200 pF = 1 X 102 X 2 X 1010 = 2 X 108 = 20 X 109 = 20 ns Rise time estimate: RP X CL = 200 X 200 pF = 2 X 102 X 2 X 1010 = 4 X 108 = 40 X 109 = 40 ns Propagation Propagation Delay
Definition Definition: The electrical path from a particular input signal of a logic element to its output signal is called a signal path signal Definition Definition: The amount of time it takes for a time change in an input signal to cause a corresponding corresponding change in a gate’s output signal signal is called the propagation delay (tp) propagation The The propagation delay for an output signal going from LOWtoHIGH (tPLH) may be LOW todifferent than the propagation delay of that signal going from HIGHtoLOW (tPHL) HIGH to Propagation Delay
Ignoring rise and fall times Measured at midpoints of transitions Propagation Propagation Delay
Several Several factors lead to nonzero nonpropagation delays in CMOS circuits: – the rate at which transistors change state is influenced both by semiconductor physics and the circuit environment (input signal signal transition time, input capacitance, and and output loading) – multistage devices (e.g., noninverting nongates) may require several internal transistors to change state before the output can change state Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly’s definition = 2 ns (30%70%) Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly’s definition = 2 ns (30%70%) Rise time (tTLH) based on standard 10%90% definition = 3.5 ns Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly’s definition = 2 ns (30%70%) Rise time (tTLH) based on standard 10%90% definition = 3.5 ns Fall time (tTHL) based on Wakerly’s definition = 1 ns (70%30%) Example
Find each of the following, rounded to the nearest ½ ns (assume each division is 1 ns) Rise propagation delay (tPLH) = 3 ns Fall propagation delay (tPHL) = 1.5 ns Rise time (tTLH) based on Wakerly’s definition = 2 ns (30%70%) Rise time (tTLH) based on standard 10%90% definition = 3.5 ns Fall time (tTHL) based on Wakerly’s definition = 1 ns (70%30%) Fall time (tTHL) based on standard 90%10% definition = 2.5 ns Power Power Consumption
Definition Definition: The power consumption (dissipation) of a CMOS circuit whose output not static is not changing is called static (quiescent) (quiescent) power dissipation Most Most CMOS circuits have very low static very power power dissipation CMOS CMOS circuits only dissipate a significant transitions amount of power during transitions – this is called dynamic power dissipation dynamic Power Power Consumption
Sources Sources of dynamic power dissipation: – the partial “shortcircuiting” of the CMOS “shortoutput structure (e.g., when the input voltage is not close to one of the power supply rails) – called “PT” (power due to output transitions output transitions) – the capacitive load on the output (power is dissipated in the “on” resistance of the active transistor to charge/discharge the capacitive load) – called “PL” (power due to charging/discharging load) load Power Power Consumption
Total Total dynamic power dissipation (PT + PL) is proportional to the square of the power square supply voltage times the transition frequency Conclusions: Conclusions: – power dissipation increases linearly as the linearly frequency frequency of operation increases – reducing the power supply voltage results in a quadratic reduction of the power quadratic dissipation Example Example
A microcontroller dissipates 100 mW of microcontroller 100 power when operated at a clock frequency 10 of 10 MHz. What will be its power dissipation if the clock frequency is reduced to 2 MHz? to MHz Answer: 2/10 X 100 mW = 20 mW Example Example
A microcontroller dissipates 100 mW of microcontroller 100 power when operated at a supply voltage of 5 VDC. What will be the its power VDC dissipation if the supply voltage is reduced to 3 VDC? to VDC Answer: (3/5)2 X 100 mW = 36 mW Clicker Quiz 1. Assume a CMOS microprocessor dissipates 100 milliwatts of power when operated at a clock frequency of 100 MHz with a supply voltage of 5 V. If the frequency of operation is reduced from 100 MHz to 40 MHz (and the supply voltage remains 5 V), the power dissipation will be reduced to: A. 16 mW B. 25 mW C. 40 mW D. 64 mW E. none 2. Assume a CMOS microprocessor dissipates 100 milliwatts of power when operated at a clock frequency of 100 MHz with a supply voltage of 5 V. If the supply voltage is reduced from 5 V to 4 V (and the frequency of operation remains 100 MHz), the power dissipation will be reduced to: A. 16 mW B. 25 mW C. 40 mW D. 64 mW E. none 3. Assume a CMOS microprocessor dissipates 100 milliwatts of power when operated at a clock frequency of 100 MHz with a supply voltage of 5 V. If the frequency of operation is reduced to 1 Hz (and the supply voltage remains 5 V) , the power dissipation will be reduced to: A. 16 mW B. 25 mW C. 40 mW D. 64 mW E. none 4. The rise time for the inverter is approximately: A. 1.0 ns B. 1.5 ns C. 2.0 ns D. 3.0 ns E. none 4. The rise time for the inverter is approximately: A. 1.0 ns B. 1.5 ns C. 2.0 ns D. 3.0 ns E. none 5. The fall propagation delay for the inverter is approx: A. 1.0 ns B. 1.5 ns C. 2.0 ns D. 3.0 ns E. none 5. The fall propagation delay for the inverter is approx: A. 1.0 ns B. 1.5 ns C. 2.0 ns D. 3.0 ns E. none 2009 2009 Edition © by D. G. Meyer Introduction to Digital System Design Module 1E Other CMOS Input/Output Structures and Logic Families Reading Reading Assignment: 3rd Ed., pp. 123142, 149154, 166171; 1231491664th Ed., pp. 129154, 158170 129158Instructional Objectives:
To To learn about specialized CMOS circuit structures, structures, including: – Schmitttrigger inputs Schmitt– threestate outputs three– open drain outputs To To learn what wired logic is and how it works To To lean how to interface TTL and CMOS gates Outline Outline
Overview Overview SchmittSchmitttrigger inputs TriTristate outputs Open Open drain outputs Driving Driving LEDs Wired Wired logic CMOS/TTL CMOS/TTL interfacing Overview Overview
The The basic CMOS circuit has been “tailored” in many ways to produce gates for specific applications This This circuit tailoring has been motivated by the need for: – higher performance than can be achieved with “standard” NAND/NOR gates – “conditioning” noisy, slowly changing logic signals – allowing logic elements to communicate via buses SchmittSchmittTrigger Inputs
Definition Definition: A Schmitt trigger is a special Schmitt circuit that shifts the switching threshold depending on whether the input is changing from LOWtoHIGH or from HIGHtoLOW LOWtoHIGHtoThe The difference between the two thresholds is called hysteresis called hysteresis
Symbol used to denote hysteresis Comparison Comparison of an Ordinary Inverter to a Schmitt Trigger for a Noisy, Slowly Changing Input Signal Regular Inverter Schmitt trigger Comparison Comparison of an Ordinary Inverter to a Schmitt Trigger for a Noisy, Slowly Changing Input Signal Regular Inverter Schmitt trigger SchmittSchmittTrigger Inputs
Observations: Observations: – Schmitttrigger inputs have better noise Schmittbetter immunity margin than ordinary gates for noisy noisy or slowly changing signals – “Distorted” logic signals of this type typically typically occur in physically long physically connections, such as I/O buses and computer interface cables Rule of “foot” – Logiclevel signals can be sent reliably over a cable for only a few feet ThreeThreeState Logic
Definition Definition: A gate output that has a third “electrical state” is called a threestate threeoutput output (or tristate output) trioutput This This third electrical state is called the high high Hifloating impedance, HiZ, or floating state In In the high impedance state, the gate output effectively appears to be disconnected from disconnected the rest of the circuit ThreeThreestate devices have an extra input, typically called the Output Enable (OE), for Output enabling data to “flow through” the device (when asserted) or placing the output in the high impedance state (when negated) CMOS ThreeCMOS ThreeState Buffer
L L L
The most common use of these devices is to create data buses (collection of signal lines) over which computational subsystems can (bidirectionally) send and receive data H HiZ Hi CMOS ThreeCMOS ThreeState Buffer
H L H
The most common use of these devices is to create data buses (collection of signal lines) over which computational subsystems can (bidirectionally) send and receive data H L CMOS ThreeCMOS ThreeState Buffer
H H L
The most common use of these devices is to create data buses (collection of signal lines) over which computational subsystems can (bidirectionally) send and receive data L H OpenOpenDrain Outputs
Definition Definition: A CMOS output structure that does not include a pchannel transistor is pcalled an opendrain output openAn openAn opendrain output is in one of two states: LOW LOW or “open” (i.e., disconnected) “open” An underscored An underscored diamond is used to indicate that an output is open drain An openAn opendrain output requires an external pullup resistor to passively pull it high in the passively “open” state (since the output structure active does NOT include a pchannel active pullup) p OpenOpenDrain CMOS NAND Gate H H Symbol that denotes an opendrain output OpenOpenDrain Gate Driving a Load
Note: Rise time of an opendrain output is much slower than that of a standard gate Driving Driving LEDs
One One application for opendrain outputs is opendriving lightemitting diodes (LEDs) light R = (VCC – VOL – VLED) / ILED
This is OHM’S LAW Driving Driving LEDs
Standard Standard CMOS gate outputs can also be used to drive LEDs, either by “sinking” current (LOW) or “sourcing” current (HIGH) Question: Which method is preferred? Example: Based on the data provided in Table 33
of the course text, calculate the value of the LED current limiting resistor for the worst case current sinking configuration. Also calculate the amount of power dissipated by the current limiting resistor. Assume VLED is 1.9 volts. Table 3.3 from DDPP SOLUTION:
VR = 5.0 – VLED – VOL = 5.0 – 1.9 – 0.33 = 2.77 V NOTE: Here, use “Max” value indicated for VOL of 0.33 V R = VR/IOL = 2.77/0.004 = 693 Ω PR = R x IOL2 = 693 x (0.004)2 = 11.1 milliwatts NOTE: Can also calculate power dissipation of resistor using VR x IOL or (VR2)/R 4.0 mA 0.33 VDC Example: Based on the data provided in Table 33
of the course text, calculate the value of the LED current limiting resistor for the worst case current sourcing configuration. Also calculate the amount of power dissipated by the current limiting resistor. Assume VLED is 1.9 volts. Table 3.3 from DDPP SOLUTION:
VR = VOH – VLED = 3.84 – 1.9 = 1.94 V NOTE: Here, use “Min” value indicated for VOH of 3.84 V R = VR/IOH = 1.94/0.004 = 485 Ω PR = R x IOH2 = 485 x (0.004)2 = 7.8 milliwatts NOTE: Can also calculate power dissipation of resistor using VR x IOH or (VR2)/R 4.0 mA 3.84 VDC Clicker Quiz DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH – VOL)/2 VOH = 3.50 V IOH = −5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 µA IIL = −2.0 mA 1. 1. When interfacing an LED that has a forward
voltage of 1.5 V to this logic family in a current sourcing configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value:
A. 200 B. 300 C. 400 D. 500 E. none of these DC Characteristics of a Hypothetical Logic Family
VCC = 5 V VTH = (VOH – VOL)/2 VOH = 3.50 V IOH = −5.0 mA VOL = 0.50 V VIH = 2.50 V IOL = 10 mA VIL = 1.00 V IIH = 500 µA IIL = −2.0 mA 2. 2. When interfacing an LED that has a forward
voltage of 1.5 V to this logic family in a current sinking configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value:
A. 200 B. 300 C. 400 D. 500 E. none of these Wired Wired Logic
Definition Wired Definition: Wired logic is performed if the outputs of several opendrain gates are tied opentogether with a single pullup resistor pull NOT an actual gate! Caution: This ONLY works for opendrain outputs! Illustration of “Fighting” Illustration Illustration of what happens if two ordinary CMOS gate outputs are tied together (don’t try this at home!) PullPullup Resistors
In openIn opendrain applications, two calculations bracket the allowable values of the pullup pullresistor R: – LOW The sum of the current through R plus the LOW state input currents of the gate gate inputs driven must not exceed the must IOLmax of the active device – HIGH The voltage drop across R in the The HIGH state must not reduce the output must voltage below the VIHmin of the driven gate inputs Pullup Resistor Calculation
High State
Here, the pullup resistor must be no more than the value Rmax such that the voltage drop across it does not exceed 5.0 – 2.4 = 2.6 V when 60 µA of current is flowing through it. Applying Ohm’s Law , we find that Rmax is 2.6/0.00006 = 43,333 ohms. Pullup Resistor Calculation
Low State
Here, the constraint is that the pullup resistor must be chosen such that the voltage drop across it must be at least 5.0 – 0.4 = 4.6 V when 3.2 mA is flowing through it. Applying Ohm’s Law, we find that Rmin is 4.6/0.0032 = 1438 ohms. 1438 ≤ R ≤ 43,333 Example: Given the following circuit, with all of its inputs connected to a LOW logic level:
VCC R L L
1 3 2 7403 1 2 O.D. 7404 L L 1 3 2 7403 O.D. If the offstate leakage current of each of the 74x03 opendrain NAND gate outputs is 5 µA, and the IIH required by the 74x04 inverter is 90 µA, determine the value of the pullup resistor R to obtain a VIH of 4.9 V at the 74x04 input. Solution:
VCC 5.0 VDC 4.9 VDC
1 2 100 µA
L L
1 3 2 7403 R O.D. 7404 L L 1 3 2 7403 90 µA 5 µA O.D. Current through R = IR = 5 µA + 5 µA + 90 µA = 100 µA Voltage drop across R = VR = 5.0 – 4.9 = 0.1 R = VR/IR = 0.1/0.0001 = 1000 Ω Clicker Quiz VCC = 5 VDC R H H 1 3 2 74HC03 1 2 O.D.
7404 7404 Assume that measurements taken in laboratory reveal that a 74HC03 (opendrain CMOS NAND gate) will produce a VOL = 0.2 V when sinking +2 mA of current. Also, assume that the IIL required by a 7404 (standardseries TTL inverter) to recognize a logic “0” is 0.4 mA and that its IIH (to recognize a logic “1”) is +40 µA. 1. Based on the laboratory measurements cited in the figure, what is the “ON” resistance of the 74HC03’s active output device? A. 10 B. 20 C. 100 D. 1000 E. none of the above 2. If the capacitive load on the output of the NAND gate is 20 pF, estimate the fall time of the signal at the input to the inverter (assuming “ON” resistance calculated in previous problem): A. 2 ns B. 16 ns C. 20 ns D. 160 ns E. none of the above 3. Calculate the value of the pullup resistor that allows the opendrain NAND gate to produce a VOL = 0.2 V when sinking 2 mA of current (i.e., IOL = +2 mA) and OL pulling the input of the 7404 low. A. 1000 B. 2000 C. 3000 D. 8000 E. none of the above 4. If the capacitive load on the output of the NAND gate is 20 pF, estimate the rise time of the signal at the input to the inverter (assuming pullup resistor value calculated in previous problem): A. 2 ns B. 16 ns C. 20 ns D. 60 ns E. none of the above 5. Assuming that the offstate leakage current of the 74HC03 is +10 µA, calculate the value of the pullup resistor resistor that produces a VIH = 4.5 V at the 7404 input. A. 4000 B. 9000 C. 10,000 D. 90,000 E. none of the above CMOS/TTL CMOS/TTL Interfacing
A typical system design may contain a typical mixture of CMOS and/or TTL families, due to: – parts availability – special requirements It It is important for a designer to understand the the implications of connecting TTL outputs to CMOS inputs, and vice versa Factors Factors to consider: – DC noise margin – fanout fan– capacitive loading CMOS/TTL CMOS/TTL Interfacing
All All of the CMOS (and TTL) devices that we will discuss have part numbers of the form: 74FAMnn
where “FAM” is an alphabetic mnemonic “FAM” and nn is a numeric function designator nn Devices Devices in different families with the same nn perform the same function nn The The prefix “74” has no social significance (it “74” was “made popular” by Texas Instruments) The The prefix “54” is used to signify “milspec” “54” “milparts (wider temperature range) TTL/CMOS Input/Output Levels Review Review Quiz “Digital Jeopardy”  1
IImax The ______ The maximum input current for any input
value of input voltage CINmax The maximum capacitance of an iinput capacitance nput ______ The VILmax The maximum voltage that an iinput ______ The voltage nput
is guaranteed to recognize as LOW LOW VIHmin The minimum voltage that an iinput is ______ voltage nput
guaranteed to recognize as HIGH HIGH Review Review Quiz “Digital Jeopardy”  2
IOLmaxC The maximum current that an output _______ The
can supply in the LOW state while LOW driving a CMOS load CMOS IOLmaxT The maximum current that an output _______ The can can supply in the LOW state while LOW driving TTL driving a TTL load VOLmaxC The maximum voltage that a LOW _______ The LOW output is guaranteed to produce CMOS driving a CMOS load VOLmaxT The maximum voltage that a LOW _______ The LOW output output is guaranteed to produce TTL driving a TTL load Review Review Quiz “Digital Jeopardy”  3
IOHmaxCThe maximum current that an output _______ The
can supply in the HIGH state while HIGH driving a CMOS load CMOS IOHmaxT The maximum current that an output _______ The can can supply in the HIGH state while HIGH state driving TTL driving a TTL load VOHminC The minimum voltage that a HIGH _______ The HIGH output output is guaranteed to produce CMOS driving a CMOS load VOHminT The minimum voltage that a HIGH _______ The HIGH output is guaranteed to produce TTL driving a TTL load ...
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