Lecture2

Lecture2 - I ns truction S t Archite e cture& Pipe lining C...

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1 Click to edit Master subtitle style Instruction Set Architecture & Pipelining CS 505: Computer Architecture Fall 2010 Abhishek Bhattacharjee
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2 Computer Science, Rutgers CS 505: Computer Structures Logistics Check course webpage for schedule regularly HW1 (Oct 4), HW2 (Oct 18), HW3 (Nov 29) – 1 week Hand in at the beginning of class (no credit for late submissions) Midterm – November 1, 2010 (1.5 hours, closed book) Final – Dec 13th, 2010 (class time)?
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3 Computer Science, Rutgers CS 505: Computer Structures Course Project Groups of 3 (tell me your group by 20th September) Mid-point Milestone (Oct 25): Implementation of 2-level cache model for a uniprocessors Your model should faithfully simulate cycle-level timing Find the specific cache parameters that are optimized for 3 SPEC benchmarks we give you (mcf, lbm, gcc) Written report (3 pages) Final Milestone (Dec 6): Implementation of extension to cache model with something from class Eg. Advanced caching, coherence, virtual memory system etc. Final presentations (~10 minute) and written report (5 pages)
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4 Computer Science, Rutgers CS 505: Computer Structures Course Project Common platform: Open source IA-32 emulation called Bochs http://bochs.sourceforge.net Functional simulator with hooks where you can add a cycle-level model Quick note: Functional versus Timing versus Trace-driven Simulation
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5 Computer Science, Rutgers CS 505: Computer Structures Instruction Set Architecture (ISA) instruction set softwar e hardwar e
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6 Computer Science, Rutgers CS 505: Computer Structures Instruction Set Architecture (ISA) softwar e instruction set hardwar e Higher-Level Languages compil er
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7 Computer Science, Rutgers CS 505: Computer Structures Classes of ISAs
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8 Computer Science, Rutgers CS 505: Computer Structures Review: Basic ISA Classe Accumulator: 1 address add A acc acc + mem[A] 1+x address addx A acc + mem[A + x] Stack: 0 address add tos tos + next General Purpose Register: 2 address add A B EA(A) EA(A) + EA(B) 3 address add A B C EA(A) EA(B) + EA(C) Load/Store:
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9 Computer Science, Rutgers CS 505: Computer Structures Evolution of Instruction Sets Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation High-level Language Based Concept of a Family (B5000 1963) (IBM 360 1964) General Purpose Register Machines Complex Instruction Sets Load/Store Architecture RIS C (Vax, Intel 432 1977-80) (CDC 6600, Cray 1 1963-76) (Mips,Sparc,HP-PA,IBM RS6000, . . .1987)
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10 Computer Science, Rutgers CS 505: Computer Structures Why L/S GPRs?? 1. Memory traffic reduction 1. Compiler allocates variables to registers effectively 1. Better encoding density (name register with fewer bits than memory location) 1. Overall code density? Jury out on this one…
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11 Computer Science, Rutgers CS 505: Computer Structures Issues in Instruction Set Design Opcodes Memory addressing Type and size of operands Encoding Implementation (pipelining, exploiting ILP)
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12 Computer Science, Rutgers CS 505: Computer Structures Addressing Modes Too many to count?
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Lecture2 - I ns truction S t Archite e cture& Pipe lining C...

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