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Unformatted text preview: Quartus Tutorial 3 Hierarchical Designs A step-by-step tutorial using Quartus II v9.0 by Gregory L. Moss Example 5-1 Tutorial * Design a 1-out-of-4 data selector circuit using a circuit design for a 1-out-of-2 data selector. A data selector uses a control input to select a single data input (from several choices) to be routed to the output of the circuit. See Fig. 5-2 and Table 5-1. If the control SEL is low, then output Y = D0 ; otherwise Y = D1 . A data selector is also called a multiplexer. Y SEL D0 D1 Fig. 5-2 1-out-of-2 data selector circuit for Example 5-1 SEL Y 0 D0 1 D1 Table 5-1 Truth table for 1-out-of-2 data selector circuit A 1-out-of-4 data selector can be constructed by combining two levels of the 1-out-of-2 data selector circuit design (see Fig. 5-3). This design can be easily implemented in a hierarchical fashion. Open the Quartus Hierarchical file in the Tutorials folder on the CD-ROM and follow the step-by-step procedures. data_sel2 SEL D0 D1 Y data_sel2 SEL D0 D1 Y data_sel2 SEL D0 D1 Y D0 D1 D2 D3 S1 S0 Y Fig. 5-3 Block diagram for 1-out-of-4 data selector circuit * You should have completed Tutorials 1 and 2 prior to using this tutorial. This example is from Unit 5 Creating Hierarchical Logic Circuits in the Digital Systems Lab Manual: A Design Approach (11 th edition) by Gregory L. Moss. 1 Copyright 2009 by Gregory L. Moss Quartus II Hierarchical Tutorial Quartus II v9.0 procedures for Example 5-1 Start a New Design Project for the Lowest-Level Block(s) 1. Start Quartus II. The main screen will open. Start the New Project Wizard by clicking the Create a New Project button on the Getting Started window. You can also start the New Project Wizard by double-clicking Open New Project Wizard in the expanded Start Project task folder in the Full Design Flow Tasks Pane. The New Project Wizard: Introduction window will open. Click the Next button. This example procedure will enter the hierarchical design as multiple projects. Start with the lowest level blocks and then work your way up to the top-level block. The lowest-level block in this example is the circuit in Fig. 5-2. Each different block design will be represented as a new project. Hierarchical designs may also be entered as a single project but lower level block testing is more difficult. 2. The Directory, Name, Top-Level Entity dialog box opens. Use computer resources specified by your lab instructor. The working directory for this project is example5_1a . The project is named data_sel2 . The Wizard will automatically copy the project name as the top-level design entity name for this project. Each project will have one top-level design entity. A new directory (folder) should be created for each separate design project. There will be many files associated with a project and they should all be placed in the same folder. Do not use duplicate design file names in a project. Click the Next button. Click Yes to create the directory....
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This note was uploaded on 10/24/2010 for the course ECET 109 taught by Professor Tocci during the Spring '10 term at Indiana State University .
- Spring '10