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Practice Test 1

Practice Test 1 - Fe.“ 1000 Si\lO EMEE R44 Aoch...

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Unformatted text preview: Fe.“ 1000 Si\lO EMEE R44 Aoch t‘bfpﬂ “1’00 -1- NAME: C. WW‘EL‘ P ) l. (20 points) Consider the synchronous sequential circuit whose logic block diagram is shown below, consisting of one negative edge-triggered RS flip—flop in which state variable qEl is stored and one negative edge—triggered JK ﬂipaflop in which state variable qb is stored. The input X is a synchronized level signal, and the output is Y. clock a. ( 4 pts) Is this a Mealy machine or a Moore machine? (Circle correct answer) j .3 a mom at I . MOORE b. (9 pts) Complete the next state and output portions of the folloMngstate transition (or ‘system design truth) table for the above logic circuit. _ ) QC’O QCEH) +9 ”i 3 - C. 913510.“; i n 7 F j b M”: a :- 3 (lug _ y, , 2h. 6“; (iii 4-3L'} b iti: is J ac’ , 1 IL' (SAL) Cw P'i'lt (in. \$ t? “7 c. ( 7 pts) Draw and correctly 1 bel (includilig inputs and outputs where they belong) the state diagram that describes the operation of the above logic circuit. ’1 1 Oo\l/ “vault {owl-PW 091/“ \/® Qaq'b {\{0 /"'—“‘9 (”W KJY’ —2k NANIE: —3— NAB/IE: 3. (15 points) Complete the speciﬁcation of the system design truth table for the design of a syn- chronous counter to be implemented with T masterwslave flip—flops that counts in the natural binary coded decimal sequence 0, 2, 6, 3, 7, and repeat on receipt of successive clock pulses. Your task is to ﬁll in the columns associated with the coded next state variables and the ﬂip—flop driving functions as though you were going to complete the design using an ablolutely minimal number of gates; however, DO NOT map the ﬂip-flop driving fuctions, obtain simpliﬁed expressions, or draw the ﬁnal logic circuit diagram. Simply ﬁll in the columns of the system design truth table. For your reference the state diagram for this counter is given below. (The high order bit is q. and the low order bit is qt.) 4. (15 points) Construct the state table for the following single—input single—output synchronous sequential system: the system produces a 1 output whenever the present input X(t) and the We previous inputs X(t-I) and X(t—2) exhibit the pattern X(t)X(t—1)X(t-2) = 101. Let the synchronized level signal input be X and the output be Y. The output is to be 0 otherwise. Also, although we don't need to worry about it in specifying the operation of the state table, if it comforts you, assume that the initial state is D so that the ﬁrst synchronizing clock pulse samples the ﬁrst input and the system does not produce a spurious output of 1 before seeing the third input symbol. u . . . . . l State Assiggment: Let the followmg states remember the followmg mformanon \ o a Let state A remember that X(t—1) = 1 and X(t-2) Let state B remember that X(t—1) = 0 and X(t-2) Let state C remember that X(t-l) = 1 and X(t—2) Let state D remember that X(t-1) = 0 and X(t-2) P H II II ll DOHH State Table: Next State versus Input X(t) X=0 X=1 -4- NAME: 5. (8 points) A negative edgeitriggered FG ﬂip—ﬂop has the characteristic truth table shown below. Produce the input excitation table for this device so we can design synchronous se uential circuits with it. . ,c q 1th acute-m Lolou Ht) 6“) QCt) Q(t+1) ecu QUH" Fci) Gd)- 6. (9 points) Using a 4 to 1 multiplexer and some additional logic the following circuit (i.e., logic block diagram) has been obtained. What switching function does this implement? Express your answer by specifying the (decimal shorthand) minterms included in the function by circling the appropriate decimal numbers on the following list. ANSWER: / / / / /' . — /, f(a,b,c,d)=}3 0 1 @@® 5 6 7 ®Gj® ll r1?) [3 14 15.? c d -5— NAME: 7. (8 points) Show how to implement the switching function f(a,b,c,d) = El,3,6,10,12 using one 4 to 1 multiplexer module, the constant inputs of zero and one, and a minimal number of NAND gates. Assume that variables a and d have been chosen as selection inputs, connected as shown. (Both complemented and uncomplemented inputs are available.) f(a,b,c,d) a. r F * I 1 l I be\ _.n l a a ...
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