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Chapter 6 - digital 2

# Chapter 6 - digital 2 - Chapter 6 Digital Electronics II...

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Chapter 6 Digital Electronics II EE4313 Electronic Circuits II

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NOR Gates Chap 6 - 2 Simplified switch model for the NOR gate with A on Two-input NOR gate
NAND Gates Two-input NAND gate (left) Chap 6 - 3 Simplified switch model for the NOR gate with A and B on (right)

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NAND Gate Device Size Selection The NAND switching transistors can be sized based on the depletion-mode load inverter To keep the low voltage level comparable with the inverter, the desired R on of M A and M B must be 0.5R on of M S,Inverter This can be accomplished by approximately doubling Chap 6 - 4 (W/L) A and (W/L) B The sizes can also be chosen by using the design value of V L and using the following equation: i D = K n ' W L S v GS V TN 0.5 v DS ( ) v DS K n ' W L S v GS V TN ( ) v DS
NAND Gate Device Size Selection (cont.) Two sources of error that arise are the facts that the V SB ’s and V GS ’s of the two transistors are not equal. These factors should be considered for proper gate design Chap 6 - 5 The technique used to calculate the size of the load transistor for the NAND gate is exactly the same as for the depletion-load inverter

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Layout of the NMOS Depletion-Mode NOR and NAND Gates Chap 6 - 6
Complex NMOS Logic Design An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates The circuit in the Chap 6 - 7 figure has the logic function: Y = A + BC + BD

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Complex Logic Gate Transistor Sizing There are two ways to find the W/L ratios of the switching transistors 1) Use the worst-case path (most devices in series) and Chap 6 - 8 choose the W/L ratios to achieve the value of R on equivalent to that of the inverter 2) Partitioning the circuit into a series sub-networks, and make the equivalent on-resistances equal
Complex Logic Gate Transistor Sizing The figure on the left shows the worst case technique to find the sizes where (W/L) S = 2.06 is the reference inverter ratio for this technology and Chap 6 - 9 the longest path is 3 transistors are in series The figure on the right shows the partitioning technique to find the sizes which gives two 4.12/1 ratios in series which is 2(2.06/1)

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Static Power Dissipation Static Power Dissipation is the average power dissipation of the logic gate for the high and low logic states: 2 DDL DD DDH DD av I V I V P + = Chap 6 - 10 I DDH = current in the circuit for v O = V H I DDL = current in the circuit for v O = V L Since I DDH = 0 A for v O = V H : 2 DDL DD av I V P =
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