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Unformatted text preview: When a positive edge occurs, a register can either hold its value (if c == 0 ) or parallel load (if c == 1 ). A parallel load means the bits are read in from the input bits ( b(k-1)-0 ) and stored in the k-bits within the register. A hold means the registers do not read in the bits, but maintains the current values of the bits. A register can only change its value at most once per positive edge. When the clock is not at a positive edge, the register maintains ("holds") its value. A k-bit register always outputs its values through z(k-1)-0 ....
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This note was uploaded on 10/27/2010 for the course EE Electronic taught by Professor Ortiz during the Spring '10 term at The University of Texas at San Antonio- San Antonio.
- Spring '10