2.c Verilog Chpt 2 8_27_10 slides 1-13 sl 7 X

2.c Verilog Chpt 2 8_27_10 slides 1-13 sl 7 X - Verilog for...

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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 1 Verilog for Digital Design Chapter 2: Combinational Logic Design F 8/27/10
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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 2 AND/OR/NOT Gates
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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 3 AND/OR/NOT Gates Verilog Modules and Ports module – Declares a new type of component Named “And2" in first example above Includes list of ports (module's inputs and outputs) input – List indicating which ports are inputs output – List indicating which ports are outputs Each port is a bit – can have value of 0 , 1 , or x (unknown value) Note : Verilog already has built-in primitives for logic gates, but instructive to build them Y X F module And2(X, Y, F); input X, Y; output F; - - - module Or2(X, Y, F); input X, Y; output F; - - - Y X F X F module Inv(X, F); input X; output F; - - - vldd_ch2_And2.v vldd_ch2_Or2.v vldd_ch2_Inv.v
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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 4 AND/OR/NOT Gates Modules and Ports Verilog has several dozen keywords User cannot use keywords when naming items like modules or ports module , input , and output are keywords above Keywords must be lower case , not UPPER CASE or a MixTure thereof User-defined names – Identifiers Begin with letter or underscore (_), optionally followed by any sequence of letters, digits, underscores, and dollar signs ($) Valid identifiers: A , X , Hello , JXYZ , B14 , Sig432 , Wire_23 , _F1, F$2, _Go_$_$, _, Input Note: "_" and "Input" are valid, but unwise Invalid identifiers: input (keyword), $ab (doesn't start with letter or underscore), 2A (doesn't start with letter or underscore) Note : Verilog is case sensitive . Sig432 differs from SIG432 and sig432 We'll initially capitalize identifiers (e.g., Sig432) to distinguish from keywords Y X F module And2(X, Y, F); input X, Y; output F; ... module Or2(X, Y, F); input X, Y; output F; ... Y X F X F module Inv(X, F); input X; output F; ... vldd_ch2_And2.v vldd_ch2_Or2.v vldd_ch2_Inv.v
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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 5 AND/OR/NOT Gates Module Procedures—always One way to describe a module's behavior uses an "always" procedure always – Procedure that executes repetitively (infinite loop) from simulation start @ – event control indicating that statements should only execute when values change "(X,Y)" – execute if X changes or Y changes (change known as an event ) Sometimes called “ sensitivity list We’ll say that procedure is “ sensitive to X and Y "F <= X & Y;" – Procedural statement that sets F to AND of X, Y & is built-in bit AND operator <= assigns value to variable reg – Declares a variable data type, which holds its value between assignments Needed for F to hold value between assignments Note : "reg", short for "register", is an unfortunate name. A reg variable may or may not correspond to an actual physical register.
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2.c Verilog Chpt 2 8_27_10 slides 1-13 sl 7 X - Verilog for...

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