7. Verilog Chapter 3 X

# 7. Verilog Chapter 3 X - Verilog for Digital Design Chapter...

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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 1 Verilog for Digital Design Chapter 3: Sequential Logic Design

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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 2 Register Behavior
Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 3 Register Behavior Sequential circuits have storage Register : most common storage component N-bit register stores N bits Structure may consist of connected flip-flops I3 I2 I1 I0 Q3Q2Q1Q0 reg(4) Rst I2 I3 Q2 Q3 Q1 Q0 I1 I0 Clk 4-bit register D Q R D Q R D Q R D Q R Rst

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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 4 Register Behavior Vectors Typically just describe register behaviorally Declare output Q as reg variable to achieve storage Uses vector types Collection of bits More convenient than declaring separate bits like I3, I2, I1, I0 Vector's bits are numbered Options: [0:3], [1:4], etc. [3:0] Most-significant bit is on left Assign with binary constant (more on next slide) `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v I3 I2 I1 I0 Q3Q2Q1Q0 reg(4) Rst I3 I2 I1 I0 module Reg4(I3,I2,I1,I0,Q3,. ..); input I3, I2, I1, I0; module Reg4(I, Q, . ..); input [3:0] I; I: I[3]I[2]I[1]I[0]
Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 5 Register Behavior Constants Binary constant 4'b0000 4: size, in number of bits 'b: binary base 0000: binary value Other constant bases possible d: decimal base, o: octal base, h: hexadecimal base 12'hFA2 'h: hexadecimal base 12: 3 hex digits require 12 bits FA2: hex value Size is always in bits, and optional 'hFA2 is OK For decimal constant, size and 'd optional 8'd255 or just 255 In previous uses like “A <= 1;” 1 and 0 are actually decimal numbers. ‘b1 and ‘b0 would explicitly represent bits Underscores may be inserted into value for readability 12'b1111_1010_0010 8_000_000 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v I3 I2 I1 I0 Q3Q2Q1Q0 reg(4) Rst

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Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 6 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule Register Behavior Procedure's event control involves Clk input Not the I input. Thus, synchronous "posedge Clk" Event is not just any change on Clk, but specifically change from 0 to 1 (positive edge) negedge also possible Process has synchronous reset Resets output Q only on rising edge of Clk Process writes output Q Q declared as reg variable, thus stores value too vldd_ch3_Reg4.v I3 I2 I1 I0 Q3Q2Q1Q0 reg(4) Rst
Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky 7

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7. Verilog Chapter 3 X - Verilog for Digital Design Chapter...

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