11. Verilog Chpt 4 - Verilog for Digital Design Chapter 4:...

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1 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Verilog for Digital Design Chapter 4: Datapath Components
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2 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Multifunction Register Behavior
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3 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Multifunction Register Behavior Previously-considered register loaded on every clock cycle Now consider register with control inputs, such as load or shift Could describe structurally Four flip-flops, four muxes, and some combinational logic (to convert control inputs to mux select inputs) We'll describe behaviorally I2 I3 Q2 Q3 Q1 Q0 I1 I0 Clk 4-bit register D Q R D Q R D Q R D Q R Rst Maintain present value Shift left Shift right Shift right – Shr has priority over Shl Parallel load Parallel load – ld has priority Parallel load – ld has priority Parallel load – ld has priority Operation Shl Shr Ld 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q2 Q1 Q0 Q3 Shr_in Shr Shl Ld Shl_in Rst Maintainvalue Shift left Operation Ld Shr Shl 0 1 0 0 0 0 Parallel load X X 1 Shift right X 1 0 Compact register operation table, clearly showing priorities
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4 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky `timescale 1 ns/1 ns module MfReg4(I, Q, Ld, Shr, Shl, Shr_in, Shl_in, Clk, Rst); input [3:0] I; output [3:0] Q; input Ld, Shr, Shl, Shr_in, Shl_in; input Clk, Rst; reg [3:0] R; always @(posedge Clk) begin if (Rst == 1) R <= 4'b0000; else if (Ld == 1) R <= I; else if (Shr == 1) begin R[3] <= Shr_in; R[2] <= R[3]; R[1] <= R[2]; R[0] <= R[1]; end else if (Shl == 1) begin R[0] <= Shl_in; R[1] <= R[0]; R[2] <= R[1]; R[3] <= R[2]; end end assign Q = R; endmodule Multifunction Register Behavior Use if-else-if construct else-if parts ensure correct priority of control inputs Rst has first priority, then Ld, then Shr, and finally Shl Shift by assigning each bit Recall that statement order doesn't matter Use reg variable R for storage Best not to try to use port Q – good practice dictates not reading a module's output ports from within a module Use continuous assignment to update Q when R changes Identifier on left of "=" must be a net, not a variable Maintainvalue Shift left Operation Ld Shr Shl 0 1 0 0 0 0 Parallel load X X 1 Shift right X 1 0 vldd_ch4_MfReg4.v
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5 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Multifunction Register Behavior Testbench should test numerous possible loads and shifts Testbench shown is brief Resets register to 0000 Loads 1111 Shifts right, shifting in 0 Continues shifting right Eventually register is 0000 ... // Clock Procedure ... // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; Ld_s <= 0; Shr_s <= 0; Shl_s <= 0; Shr_in_s <= 0; Shl_in_s <= 0; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; Ld_s <= 1; @(posedge Clk_s); #5 Ld_s <= 0; Shr_s <= 1; // Good testbench needs more vectors end endmodule vldd_ch4_MfReg4TB.v I_s Q_s Ld_s Shr_s Shl_s Shr_in_s Shl_in_s Clk_s Rst_s 0 10 20 30 40 50 60 70 80 90 100 110 120 time (ns)
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6 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Multifunction Register Behavior Question : Does the
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This note was uploaded on 10/27/2010 for the course ECE 220 taught by Professor Strickland during the Spring '08 term at University of Arizona- Tucson.

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11. Verilog Chpt 4 - Verilog for Digital Design Chapter 4:...

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