Chapter 2 HW Solutions X

Chapter 2 HW Solutions X - CHAPTER 2 COMBINATIONAL LOGIC D...

This preview shows pages 1–3. Sign up to view the full content.

13 CHAPTER 2 COMBINATIONAL LOGIC DESIGN 2.1 EXERCISES Any problem noted with an asterisk (*) represents an especially challenging problem. Section 2.2: Switches 2.1. A microprocessor in 1980 used about 10,000 transistors. How many of those micro- processors would fit in a modern chip having 3 billion transistors? 3,000,000,000 / 10,000 = 300,000 microprocessors 2.2 The first Pentium microprocessor had about 3 million transistors. How many of those microprocessors would fit in a modern chip having 3 billion transistors? 3,000,000,000 / 3,000,000 = 1,000 microprocessors 2.3 Describe the concept known as Moore’s Law. Integrated circuit density doubles approximately every 18 months. 2.4 Assume for a particular year that a particular size chip using state-of-the-art technol- ogy can contain 1 billion transistors. Assuming Moore’s Law holds, how many tran- sistors will the same size chip be able to contain in ten years? Approximately 100 billion transistors (10 years * 12 months/year / 18 months/dou- bling = 6.667 doublings. 1 billion * 2 6.667 = 101.617 billion). 2.5 Assume a cell phone contains 50 million transistors. How big would such a cell phone be if the phone used vacuum tubes instead of transistors, assuming a vacuum tube has an volume of 1 cubic inch? 50,000,000 transistors * 1 in 3 /transistor = 50,000,000 in 3 (nearly 30,000 cubic feet - as large as a house)

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
14 c 2 Combinational Logic Design 2.6 A modern desktop processor may contain 1 billion transistors in a chip area of 100 mm 2 . If Moore’s Law continues to apply, what would be chip area for those 1 billion transistors after 9 years? What percentage is that area of the original area? Name a product into which the smaller chip might fit whereas the original chip would have been too big. Doubling chip capacity every 18 months also suggests halving of size every 18 months of the same number of transistors. 9 years / 18 months is 108 months / 18 months = 6 halvings. 100 mm 2 * (1/2) 6 = 100 mm 2 / 64 = 1.56 mm 2 . 1.56 mm 2 / 100 mm 2 = 1.56% of the original area. A product into which such a small chip might now fit is a hearing aid, for example. Section 2.3: The CMOS Transistor 2.7 Describe the behavior of the CMOS transistor circuit shown in Figure 2.77, clearly indicating when the transistor circuit conducts. When x is a logical 0, the top transistor will con- duct, otherwise the top transistor will not con- duct. Likewise, when y is a logical 0, the bottom transistor will conduct and not conduct other- wise. Thus, the circuit conducts only when x is 0 and y is 0. 2.8 If we apply a voltage to the gate of a CMOS transistor, why doesn’t the current flow to the transistor’s source or drain? An insulator exists between the gate and the source-drain channel, prohibiting cur- rent from flowing to the transistor’s source or drain. 2.9 Why does applying a positive voltage to the gate of a CMOS transistor cause the transistor to conduct between source and drain?
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/27/2010 for the course ECE 220 taught by Professor Strickland during the Spring '08 term at Arizona.

Page1 / 28

Chapter 2 HW Solutions X - CHAPTER 2 COMBINATIONAL LOGIC D...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online