Chapter 3 HW Solutions - CHAPTER 3 SEQUENTIAL LOGIC D ESIGN...

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41 CHAPTER 3 SEQUENTIAL LOGIC DESIGN -- CONTROLLERS 3.1 EXERCISES Any problem noted with an asterisk (*) represents an especially challenging problem. Section 3.2: Storing One Bit—Flip-Flops 3.1. Compute the clock period for the following clock frequencies. a. 50 kHz (early computers) b. 300 MHz (Sony Playstation 2 processor) c. 3.4 GHz (Intel Pentium 4 processor) d. 10 GHz (PCs of the early 2010s) e. 1 THz (1 terahertz) (PCs of the future?) a) 1/50,000 = 0.00002 s = 20 us b) 1/300,000,000 = 3.33 ns c) 1/3,400,000,000 = 294 ps = 0.294 ns d) 1/10,000,000,000 = 100 ps = 0.1 ns e) 1/1,000,000,000,000 = 1 ps 3.2 Compute the clock period for the following clock frequencies. a. 32.768 kHz b. 100 MHz c. 1.5 GHz d. 2.4 GHz a) 1/32768 = 30.5 us b) 1/100,000,000 = 10 ns c) 1/1,500,000,000 = 0.66 ns = 667 ps d) 1/ 2,400,000,000 = 0.416 ns = 416 ps
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42 c 3 Sequential Logic Design -- Controllers 3.3 Compute the clock frequency for the following clock periods. a. 1 s b. 1 ms c. 20 ns d. 1 ns e. 1.5 ps a) 1/1s = 1 Hz b) 1/.001 = 1000 Hz = 1 kHz c) 1/20ns = 50,000,000 Hz = 50 MHz d) 1 /1ns = 1,000,000,000 = 1 GHz e) 1/1.5ps = 666 GHz 3.4 Compute the clock frequency for the following clock periods. a. 500 ms b. 400 ns c. 4 ns d. 20 ps a) 1/500ms = 2 Hz b) 1/400 ns = 2,500,000 Hz = 2.5 MHz c) 1/4ns = 250,000,000 Hz = 250 MHz d) 1/20ps = 50,000,000,000 Hz = 50 GHz 3.5 Trace the behavior of an SR latch for the following situation: Q, S, and R have been 0 for a long time, then S changes to 1 and stays 1 for a long time, then S changes back to 0. Using a timing diagram, show the values that appear on wires S, R, t, and Q. Assume logic gates have a tiny nonzero delay. . S R 1 0 1 0 t 1 0 Q 1 0
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3.1 Exercises b 43 3.6 Repeat Exercise 3.5, but assume that S was changed to 1 just long enough for the sig- nal to propagate through one logic gate, after which S was changed back to 0 -- in other words, S did not satisfy the hold time of the latch. 3.7 Trace the behavior of a level-sensitive SR latch (see Figure 3.16) for the input pat- tern in Figure 3.92. Assume S1, R1, and Q are initially 0. Complete the timing dia- gram, assuming logic gates have a tiny but non-zero delay. 3.8 Trace the behavior of a level-sensitive SR latch (see Figure 3.16) for the input pat- tern in Figure 3.93. Assume S1, R1, and Q are initially 0. Complete the timing dia- gram, assuming logic gates have a tiny but non-zero delay. S R 1 0 1 0 t 1 0 Q 1 0 Figure 3.92 S C R S1 R1 Q Figure 3.93 S C R S1 R1 Q
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44 c 3 Sequential Logic Design -- Controllers 3.9 Trace the behavior of a level-sensitive SR latch (see Figure 3.16) for the input pat- tern in Figure 3.94. Assume S1, R1, and Q are initially 0. Complete the timing dia- gram, assuming logic gates have a tiny but non-zero delay. . 3.10 Trace the behavior of a D latch (see Figure 3.19) for the input pattern in Figure 3.95. Assume Q is initially 0. Complete the timing diagram, assuming logic gates have a tiny but non-zero delay. 3.11 Trace the behavior of a D latch (see Figure 3.19) for the input pattern in Figure 3.96. Assume Q is initially 0. Complete the timing diagram, assuming logic gates have a tiny but non-zero delay. Figure 3.94 S C R S1 R1 Q metastable Figure 3.95 D C S R Q Figure 3.96 D C S R Q
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3.1 Exercises b 45 3.12 Trace the behavior of an edge-triggered D flip-flop using a master-servant design (see Figure 3.25) for the input pattern in Figure 3.97. Assume each internal latch ini- tially stores a 0. Complete the timing diagram, assuming logic gates have a tiny but non-zero delay.
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Chapter 3 HW Solutions - CHAPTER 3 SEQUENTIAL LOGIC D ESIGN...

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