ENG_274_Lab_Report_Lab_1

ENG_274_Lab_Report_Lab_1 - Lab 1: Introduction to Verilog...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Lab 1: Introduction to Verilog Simulation and Synthesis Student Information: Jonathan Sooter jbsooter@gmail.com Partner: Corey Davis Lab Purpose: The purpose of this lab was to build the basic AND, OR and INV logic gates that are the basis for all combinational logical circuits. It was also designed to familiarize us with the Verilog language and simulation and synthesis in the Xilinx system. Implementation Details: The implementation of this lab consisted of first following the tutorials provided for the AND gate and then repeating the process for the OR and INV gates. The first task, after opening the Xilinx software was to write the Verilog code for the AND gate, which is as follows. `timescale 1ns / 1ps module and2gate(A, B, F); input A, B; output F; reg F; always @(A,B) begin F <= A & B; end endmodule To ensure the written code provided the correct results we made a test bench to test all the possible inputs and outputs that this code could result. The test bench code is as follows: `timescale 1ns / 1ps module and2gate_tb(); reg A_t, B_t; wire F_t;
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
and2gate and2gate_1(A_t, B_t, F_t); initial begin //case 0 A_t <= 0; B_t <= 0; #1 $display ("F_t = %b", F_t); //case 1 A_t <= 0; B_t <= 1; #1 $display ("F_t = %b", F_t); //case 2 A_t <= 1; B_t <= 0; #1 $display ("F_t = %b", F_t); //case 3 A_t <= 1; B_t <= 1; #1 $display ("F_t = %b", F_t); end endmodule Next we wrote modules and test benches for both the OR and INV gates. The following code is the OR gate module: `timescale 1ns / 1ps
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/27/2010 for the course ECE 220 taught by Professor Strickland during the Spring '08 term at University of Arizona- Tucson.

Page1 / 6

ENG_274_Lab_Report_Lab_1 - Lab 1: Introduction to Verilog...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online