Lab 3 Report - Lab 3 Report: FSM for 4-bit Up/Down Counter...

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Lab 3 Report: FSM for 4-bit Up/Down Counter Student Information: Jonathan Sooter jbsooter@gmail.com Partner: Corey Davis Lab Purpose: The purpose of this lab was to create a Finite State Machine that counts either up or down every second depending on the Up/down input switch. Since the counter has a memory of 4-bits the counter can count from 0 to 15 and is designed to wrap around when it reaches 15 counting up or 0 counting down. The lab also uses an Enable switch that pauses the counter at the current value and a reset switch that sets the counter back to 0. Implementation Details: The first thing to do when creating a Finite State Machine is to draw a state diagram. The state machine for this lab is fairly simple in that all states go to the default state of 0 when the reset is1, they stay at their current state if enable is 0, and if those two conditions aren't met every state goes to the next or previous state based on the Up/Down switch. There are 16 states, one for each possible output of the counter, 0 through 15. Next thing to do is set each state to a 4-bit value. Since the output area already a 4-bit value, each state can be conveniently set to its corresponding output so state 0000 will output 0, 0001 outputs 1, 0010 outputs 2, etc. To create the FSM in Verilog code, two always statements will be used. The first will trigger every clock cycle and update the current state to the value determined as the next state and the second always will trigger every time the state changes or the inputs change. The following is the commented Verilog code for the FSM: `timescale 1ns / 1ps module fsm_4bit_counter(input wire clk, rst, enable, up_dwn, output reg [3:0] cnt); reg [3:0] st, next_st; /* s_0 - s_F are the possible states the counter can be in. s_0 outputs 0000, s_1 outputs 0001, . .. , s_F outputs 1111. I used 'h instead of 'b because its less typing. */
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parameter s_0 = 'h0, s_1 = 'h1, s_2 = 'h2, s_3 = 'h3, s_4 = 'h4, s_5 = 'h5, s_6 = 'h6, s_7 = 'h7, s_8 = 'h8, s_9 = 'h9, s_A = 'hA, s_B = 'hB, s_C = 'hC, s_D = 'hD, s_E = 'hE, s_F = 'hF; /* This always triggers every clock cycle or whenever the reset button is pushed. If the clock cycles the st goes to whatever is defined as the next state. If reset is pushed or being held down while the clock cycles, the state is set to s_0 (0000). The posedge rst makes this always loop trigger when rst is pushed making the counter goto 0 right away instead of waiting for the next clock cycle. */ always @(posedge clk, posedge rst) begin st <= rst ? s_0 : next_st; end /* This always triggers when the state changes which happens every clock cycle the counter is enabled or when the enable or up/down inputs are changed */ always @(st, enable, up_dwn) begin // Since the state values coorespond to the output at that state // we can just set the output to the state variable. cnt <= st;
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This note was uploaded on 10/27/2010 for the course ECE 220 taught by Professor Strickland during the Spring '08 term at University of Arizona- Tucson.

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Lab 3 Report - Lab 3 Report: FSM for 4-bit Up/Down Counter...

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