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4 - Synchronous State Machine &amp; State Machine Design

# 4 - Synchronous State Machine &amp; State Machine...

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EEN 304: Logic Design 53 Analysis of Synchronous Sequential Machines Timing Chart Example 44: Analyze a Moore network shown in Fig-1, using an input sequence X=10101 B Z A X K X J B X K X J B B A A = = = = = Assistant Table X A B J A K A J B K B A + B + 1 0 0 1 1 1 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 Timing Chart: Assuming initial state A=B=0 Clock 10101 X 011110 A 011001 B 011001 Z=B J A =X=1 K A =X B=1 0=1 J A =0 K A =0 J A =1 K A =0 J A =0 K A =0 J A =1 K A =1 J B =X=1 K B =X A =1 0=0 J B =1 K B =1 J B =0 K B =0 J B =1 K B =1 J B =0 K B =0 * The output does not appear until after the clock pulse

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EEN 304: Logic Design 54 Example 45: For the state machine described by the following equations complete the time chart shown below. B X B X J A . . + = , B X K A . = , A X K J B B . = = , B A Z . = Assistant Table X A B J A K A J B K B A + B + 1 0 0 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 Time Chart Clock X A B Z Example 46: Analyze a Mealy network shown in Figure-2 using the input sequence X=10101. The input is assumed to change between clock pulses J A A K A A J B B K B B Clock X B A X B X A X A B Z
EEN 304: Logic Design 55 J A =X B K A =X J B =X K B =X A Z=X B+X A+X A B Assistant Table X A B J A K A J B K B A + B + 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 Clock X A B Z

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EEN 304: Logic Design 56 Method ° Step1: Flip-Flop Input Equations & Output Equations ° Step2: Transitions Table number of the states = 2 P where P=number of Flip-Flops ° Step3: Next-State Table & Output Table ° Step4: State Diagram Example 47: Moore Model Step1: FF Input Equations & Output Equations X J A = B X K A = X J B = A X K B = B Z = Step2: Transitions Table AB X=0 X=1 Z 00 00 11 0 01 00 11 1 10 10 01 0 11 11 10 1 A + B + X A B J A K A J B K B A + B + Z 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 Step 1 Step 2 Step 3 Step 4 Circuit State Diagram Analysis State Diagram Circuit X A B 0 0 0 J A =X=0 K A =X B=0 1=0 J B =X=0 K B =X A=0 1=1 J A A K A A J B B K B B X Z Clock
EEN 304: Logic Design 57 Step3: Next State Table Present State X=0 X=1 Z 00 = S 0 S 0 S 3 0 01 = S 1 S 0 S 3 1 10 = S 2 S 2 S 1 0 11 = S 3 S 3 S 2 1 Next State Step4: State Diagram Example 48: Step1: FF Input Equation & Output Equations J=X Y 2 K=X+Y 2 D=Y 1 Y 2 +X Y 2 Z=X Y 1 Y 2 J Y 1 K Y 1 D Y 2 Y 2 + + Y 1 Y 2 Y 2 Y 2 Y 2 X Z Clock S 0 /0 S 3 /1 S 1 /1 S 2 /0 X=0 X=0 X=0 X=0 X=1 X=1 X=1 X=1

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EEN 304: Logic Design 58 Step2 Number of states = 2 P =2 2 =4
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4 - Synchronous State Machine &amp; State Machine...

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