6 - State Machine Timing

6 - State Machine Timing - EEN 304 Logic Design State...

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EEN 304 Logic Design State Machine: Timing
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EEN 304 – Logic Design 1 Flip-Flop Parameters TTL flip-flops operate properly if all pulses applied to them are longer than 50 ns. For higher speed circuits, the following parameters specified by the manufacturer should be observed. t PLH Input t PHL Clock t su t H
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EEN 304 – Logic Design 2 Definitions 1. Setup time (t SU ): This is the time a signal must be present on one terminal before an active transition occurs at another terminal. For a 7474 1 , t SU is 20 ns (20 ). This means that the D input must be held constant for at least 20 ns before a positive clock edge to assure a reliable output. 2. Hold time (t H ): this is the time a signal must remain at the terminal after an active transition occurs. For a 7474 1 , t H is 5ns. The signal at the D input should be removed no sooner than 5 ns after the positive edge of the clock. There is zero hold time for most J-K flip-flops. 3.
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This note was uploaded on 10/28/2010 for the course EEN 304 taught by Professor Nigeljohn during the Spring '10 term at University of Miami.

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6 - State Machine Timing - EEN 304 Logic Design State...

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