CH 1 Part 2 Diode Circuits

CH 1 Part 2 Diode Circuits - Reuecse bias If " ‘...

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Unformatted text preview: Reuecse bias If " ‘ OPGM C W'ch __..0—_ I=O / burs // f/ 5/40???" CIRCUIT +5v +5“ _ 1' 35K 25,: V=? I"? J _. __o ____..,0 + 1- I + t 7 M: * VD Arca/ flow/ 5/3 7&2ng pap; {Vaéiptg 1.3,] IIIZVa‘llO-‘h I Gf‘a 9 I7L€Fq71foln rho-9.215 051g 71mg? We? 7.; [Dyna/é OLS’e‘D/U74ifi";7 749 a, Frag/9%? ., 5 GCQFLICCL/ Carma] 5n; )éC/l’mfde [flu/cy/défi f/pAé'qa! Aft-Jo s ImufiLameous étz‘rowlroms é /oca7[g 779$ [Daw‘é (912 f IW‘lETSQC'I‘Iow— 7%? 36/071109”), Emwla R f T 9 vps: 10.1; + VD .—_—_> ID: VPS ~ g“ VFS __ ID 1 VD kin/VT u R 1 $ 8 VF; Is R [evD/“i I] :- VD (9%: (PWercdfi. AWJQWF Awuscnggmwé/gfudlwfi C1710! cammmé @sdD/MCZ GIIWcilg; USE I7L6\"L77LKLC;J‘[,a R 7(9— sojmlwln 0*" @"fwmf ((fU’QSCWfi/cmmE) _z_ (lei Dc? first? IDQ R f/FWJC L VD VDC? VFS 71?, Sam uracil: d5 LeporQJ' J'13 (TEA) Diode I-V characteristics 5‘9“,— A4206— «(f/fl 1.5 Load line 1.0 0.5 o :0‘621 2 3 4 5 VB (volts) The diode and load line characteristics for the circuit shown ‘ 13%: 73:42:59le Linear HoJe/ any- )9er mm «1e. “k CLQJ@_’5 I-V cilaraclcmsmlrc-SJ a s lmfcet‘ filer-7407154 7;; as f‘ S'I'Vagkf [hips , V53 Ilvm-an 9F chl-t-L Vfl/Ildoqe Fm— VD 9V3; J a SVngM-Me “rf’wk'wmtwh mi a. slope «99 my. "FF 5 flawed 0!,ng wslsima_ fD=-IS The ideai diode l—V characteristics and two linear approximations - +__J|'_'* MAP—J 0413 rev VD 2 VF Ho 97owaf9fié culture 11;); + . I F0?“ VD < Vb, 7% QfOIVGIé’Wlé CN‘cu-é 1;; +_—D’+__._l 1-10 we 4550M fiaé T10 = OJ fzechSe. lh’l‘é'af‘ 'WIQJQ/ (4);” Jade, 71f: cgafycénsgcic/r VD Vr ngém% Var/11%;? For Us? Vr=0.¥y / O ~ . VF: 051a a. PI€C€WLS€ AWN“ 5V _“ woclel 834‘ 7% c’mJé M'H, f VF =0.6v f. TF=I0JL VD“, = Vr + 15W:- 0. 6 +(a7-qu4)(10n)= 0. 631% 716 VGLWS @L‘ildl'h-Dé 05:. 7% flechUJlg'e. hear Woo/e/ am, mega/7 FEM/70L 7%? Sv/Ulrcov'h @L'lam'ez 1510 Feeyé‘s ear/JP L953 7% W{ afromlrorm L0 m (9595 7‘12 c97151£am7§ Vfl/Ttdaq'e olm‘o 9p 4?.in IF' WP=QJL 5- 0.} = 4.6 01k “9 In“ (3 B/(iUIIESce/zt Fbfifé) \\ \ POI-13f "‘3 V P5 D C ' 19C Rasaglcmws 910 cc- Drove/e. “6/ { No+a+;wm: 1495-" cowa-Mé R 042‘; Ac, cowFo-M-nt a9 a "mu! 7mng (Dam) ID MM v m2 .392. b 1D=I5(e my? "‘0’: I58 “VT VD 111' 7‘4— Wn; i VOA”?- ID= 8 Oil]: _ l I- QVDK’VT... ID - rat: “VT :: ——(—-—-H aswv Glyn "W1: 5 ‘ 01V? ” ID. ID +£— . , mt . W5 #21 (we Lani: 1Q? a. wome-n'é '31 m #V J'OJ“ ‘27" '9'“) _7—‘ a - . _ uwr _ I vhf; UD=VD+UOLJ .. CD—Ise _ Se a» o VB/VT (lei/VT] I—P 7% a,::. sandal a; song” of @,{<<V7-0 CD: ' e exg (fix) Q? 5m” X values. 5XQWIEE Rflflk b 7&2, aimed? A475 51 ‘9' fl fjmwt WWW? = Mow} eke? ataami 1M, 'nflz Fr’hfil (flou‘é “:2 ID : l0-(p-F (ID L“; 6/05? 79' VD Q why?" “If” be 11;? Clay? 715 QF'V I3) AC flmaifigsé - I Rflflk ‘ Jr h t = Q m, VOL TDQ (9.33mi) 53' '2 , _ [3” Example 1.4-1 A junction diode is used in the circuit of Fig. 1.4—4 with Vdc=l.5V Vim=20rnV ri=10fl R1=90§2 R1L = 200 Q C = 100 ,uF co =104 rad/s Find the voltage across RL. SOLUTION To find the Q point, the dc load line is drawn through the point up = 1.5 V, with slope —-1/(r,- + R1) = —0.01. The intersection of this load line and the diode characteristic occurs at 7.5 mA and 0.75 V (Fig. 1.4—5). The location of the Q point on the curve and the size of the ac signal indicate that small-signal theory will be applicable. From (1-4-15) 25 x 10—3 r“i = —-——Ta 3 3.3 Q V__ 7.5 x 10 v . > 113‘? :5 7.5 Q Dc load line A Figure 1.4-5 Graphical evaluation of Q point for o 0.75 1.5 up. V the circuit of Fig. 1.4-4. Since |Xcl = l/wC m l 9., the capacitor is seen to have negligible impedance in comparison with RL. Taking this into account, we have ZL z Rl “RL = 62 9.“? The small-signal circuit analogous to Fig. 1.4—3b takes the form shown in Fig. 1.4-6. Using the values obtained for rd and Z L, we get VL.dc=0 Vimlztl N (20x62) iri+rd+ZL| ~10+3.3+62 mumv Van: IdmlztlF W and Figure 1.4—6 Small-signal equivalent circuit. w MW- The circuit of Fig. 1.4—4 was described in Sec. 1.4 by a combination of graphical and analytical methods. By a simple extension of the dc-load-line concept it is possible to perform both the do and ac analyses graphically as long as the reac- tance of the capacitor is negligible. This procedure leads to the concept of the ac load line, which, while not often used in practice for diode circuits, is often used to analyze and design transistor circuits. Since the concept is easier to grasp in terms of the simple diode, we introduce it at this point. For the circuit of, Fig. 1.4-4, the dc load line and Q point are obtained as shown in Fig. 1.5-1. The dc conditions are not influenced by that part of the circuit consisting of the capacitor C and load resistance RL because of the dc blocking action of the capacitor. The slope of the dc load line is therefore determined by the resistance r!— + R1. When an ac signal is present (assume that the capacitor acts as a short circuit at the frequencies involved), the effective resistance as seen by the diode is r,- .+ (R 1 HRL), which is the negative of the inverse slope of the ac load line. In order to draw this ac load line, we need only one point, since the slope is known. The point where the ac signal is zero is the easiest to obtain. This is simply the Q point. Thus the ac load line is drawn through the Q point with a slope m 1/[ri + (R1 ||RL)], as shown in Fig. 1.5—1. As the signal varies with time, the ac load line moves back and forth to define the operating path for the diode. Compare this with Fig. 1.4-1, where the dc load line moves back and forth. The difference between these two lies in the fact that ’ the ac impedance is not the same as the dc resistance seen by the diode for the circuit being considered in this section. The amplitude of the ac component of current is found using the graphical construction shown in Fig. 1.54. The operating path is along the segment a’b’ of the diode characteristic. This procedure will yield results identical with the analy- tical results obtained in (1.4-16) as long as segment a’b’ is approximately linear. As in Sec. 1.4, it is conceptually useful to superimpose a set of id-vd axes on the curves of Fig. 1.5-1. This is left as an eitercise. The equations for the do and ac load lines can be obtained simultaneously from the circuit of Fig. 1.4-4 by using KVL. We have Vet + vi = fort + “c + IDQRI + id(R1”RL) (1-5‘1) Setting ip = id + I m and up = rid + VDQ and making the reasonable assumption that superposition applies yields IQ: = I DQ(ri + R1) + VDQ dc—load-line equation (1.5-2a) and 'uf = id(r,- ~t— (JRl |[R2)) + vd ac—load-line equation , (1.5—2b) “D, mA ® cfo m‘é ff/re7é draw/q, [The (-n (Jug, I’ll 5/0 if as grimy 32% 4° . 19¢ REC :: {Ed-(EJ/R‘): = I0+(?0//Ma)= V134. T : Fl. an; 5; AV AV= Iraq, '93:: 755,..9 - FR». 06332: Figure 1.5-1 Graphical solution of the circuit of Fig. 1.4-4. 7% I‘SLVPQIMLQ 0 }S__‘ ding; 33‘ I ——u——u—4—-—+ l 2. 3 4' 49,1 e/mewé x wi/i’ dam; v-r curué 3;, Fat 01 1g “7.7.9:ch 73 4-1:. 0mm! Luz/5’ W5” 92' 2P=Ima (:52) ,9 13-?qu 7% D_C. /oaa/ /I:ne_ ED FI'RCL v): EiéIX 1%? 7g circa-15, ________._——-————--—-D-. o . Dy 3mg— Cfim 4‘ . J.Sll0_3(5z{2‘ Car 02 )0 1N1. d0] (fig 0 _ Qrfiéko / Emil-’75] SE Wt a; wall .4: m/ 9490490) B —(———————’— B) Fmd 7% @7319fo (Imp %' c.) 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This note was uploaded on 10/28/2010 for the course EEN 305 taught by Professor Lask during the Spring '10 term at University of Miami.

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CH 1 Part 2 Diode Circuits - Reuecse bias If " ‘...

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