lec04mod - CS415 Compilers Register Allocation and...

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Unformatted text preview: CS415 Compilers Register Allocation and Instruction Scheduling These slides are based on slides copyrighted by Keith Cooper, Ken Kennedy & Linda Torczon at Rice University Lecture 4 2 cs415, spring 10 A value is live between its definition and its uses Find definitions (x ) and uses (y x ...) From definition to last use is its live range How does a second definition affect this? Note: our code shape does not allow redefinition of pseudo registers Can represent live range as an interval [i,j] (in block) live on exit Let M AX L IVE be the maximum, over each instruction i in the block, of the number of values (pseudo-registers) live at i. If M AX L IVE k, allocation should be easy If M AX L IVE k, no need to reserve F registers for spilling If M AX L IVE > k, some values must be spilled to memory Finding live ranges is harder in the global case Review Live Range Lecture 4 3 cs415, spring 10 Top-down Versus Bottom-up Allocation Top-down allocator Work from external notion of what is important Assign registers in priority order Register assignment remains fixed for entire basic block (entire live range) Save some registers for the values relegated to memory (feasible set F) Bottom-up allocator Work from detailed knowledge about problem instance Incorporate knowledge of partial solution at each step Register assignment may change across basic block (different register assignments for different parts of live range) Save some registers for the values relegated to memory (feasible set F) Lecture 4 4 cs415, spring 10 Top-down Allocator The idea: Keep busiest values in a register Use the feasible (reserved) set, F, for the rest Algorithm: Rank values by number of occurrences Allocate first k F values to registers Rewrite code to reflect these choices SPILL: Move values with no register into memory (add LOADs & STOREs) Lecture 4 5 cs415, spring 10 Bottom-up Allocator The idea: Focus on replacement rather than allocation Keep values used soon in registers Algorithm: Start with empty register set Load on demand When no register is available, free one Replacement: Spill the value whose next use is farthest in the future Sound familiar? Think page replacement ... Lecture 4 6 cs415, spring 10 An Example ILOC subset: Assume a register-to-register memory model, with 1 class of registers. Latencies are important for instruction scheduling, not register allocation and assignment Operation Meaning Latency load r1 r2 MEM (r1) r2 2 store r1 r2 r1 MEM(r2) 2 loadI c r1 c r1 1 add r1, r2 r3 r1 + r2 r3 1 sub r1, r2 r3 r1 r2 r3 1 mult r1, r2 r3 r1 x r2 r3 1 lshift r1, r2 r3 r1 << r2 r3 1 rshift r1, r2 r3 r1 >> r2 r3 1 output c print out MEM(c) 1 Lecture 4 7 cs415, spring 10 An Example Here is a sample code sequence loadI 1028 r1 // r1 1028 load r1...
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lec04mod - CS415 Compilers Register Allocation and...

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