Week01_Introduction_EE4313_Fall2010

Week01_Introduction_EE4313_Fall2010 - EE4313: CE Design...

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EE4313 EE4313: CE Design Project I Class Introduction N. Sertac Artan sartan@poly.edu
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EE4313 Syllabus: People Instructor: N. Sertac Artan Office Hours: TBA Office: LC 105, Tel: (718) 260-3496, E-mail: sartan at poly edu URL: http://eeweb.poly.edu/artan TA: Vivek Pujeri Office Hours: TBA Office: TBA E-mail: vpujer01 at students poly edu 9/7/2010
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EE4313 Syllabus: Grading Class participation: 10% Quizzes: 10% (at the beginning of every lecture) Exam 1: 20% Exam 2: 20% Homework Labs: 20% VHDL models for some applications Simulation of VHDL models Download designs onto an FPGA for validation Term Project: 20% 9/7/2010
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EE4313 Syllabus: Time and Venue Class meets: Tuesdays 6 pm to 8:40 pm In JAB674 Open Lab: Last hour of the class In JAB674 9/7/2010
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EE4313 Syllabus: References and FPGA Board No textbooks Three reference books: 1. “FPGA Prototyping by VHDL Examples” by Pong P. Chu 2. “RTL Hardware Design Using VHDL” by Pong P. Chu 3. “Advanced FPGA Design” by Steve Kilts Further details about the books are on my.poly FPGA Board to purchase instead of a textbook Digilent Nexys2 FPGA Board ($99) Make sure to choose the 500K gate academic option http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 9/7/2010
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EE4313 Syllabus: Ethics Academic honesty Attend classes and labs Submit assignments on time Check your email and my.poly regularly 9/7/2010
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EE4313 EE4313/EL5493 Lecture 1: Introduction to Digital Design with VHDL N. Sertac Artan sartan@poly.edu
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EE4313 INTRODUCTION 9/7/2010
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EE4313 Introduction WHAT VHDL V ery High Speed Integrated Circuit H ardware D escription L anguage HDL=Describes behavior, data flow, structure WHY Shrinking design cycle Simulation and formal verification Synthesis Reliable design process (eliminates design errors) Documentation and requirements specification HOW
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Week01_Introduction_EE4313_Fall2010 - EE4313: CE Design...

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