Week02_EE4313_EL5493_Fall2010

Week02_EE4313_EL5493 - EE4313/EL5493 Lecture 2 N Sertac Artan sartan@poly.edu EE4313/EL5493 Last Week Top-down VHDL-based VLSI design methodology

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EE4313/EL5493 EE4313/EL5493 Lecture 2 N. Sertac Artan sartan@poly.edu
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EE4313/EL5493 Last Week: Top-down VHDL-based VLSI design methodology Functional Simulation VHDL Model Synthesis Timing verification Floorplan, placement and routing 2
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EE4313/EL5493 Last Week: OR-AND Gate Complete VHDL Model library IEEE; use IEEE.std_logic_1164.all; entity or_and is port ( a, b, c: in std_logic; o: out std_logic ); end or_and; architecture Do_it of or_and is signal D: std_logic; begin D <= A or B; O <= D and C; end Do_it; A B C D O Blackbox What it does Concurrency 3
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EE4313/EL5493 Last Week: Circular Left Rotate By One Bit library IEEE; use IEEE.std_logic_1164.all; entity Circular_rot_left_1 is port ( A : in std_logic_vector(3 downto 0); Y : out std_logic_vector(3 downto 0)); end Circular_rot_left_1; architecture Do_it of Circular_rot_left_1 is begin Y <= A(2 downto 0) & A(3); end Do_it; Alternative notation. & stands for concatenation 4
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EE4313/EL5493 VHDL OBJECT AND DATA TYPES 5
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EE4313/EL5493 VHDL Object Types General purpose programming languages have Constant Fixed value, cannot be updated Can be declared inside or outside a process Examples constant default_gate_delay: Time := 50 ps; constant coefficient: integer := 1024; Variable Used for local storage in processes, procedures and functions Can be initialized Change their values through assignment statements In VHDL, := is used for variable assignment Updated as soon as a variable assignment statement is executed Examples variable address: bit_vector(15 downto 0) := x”0000”; variable flag: boolean := FALSE; variable temperature : integer range 0 to 100 := 60; In VHDL, we also have constants and variables. Additionally we have Signal More about this later File 6
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EE4313/EL5493 VHDL Data Types The type of an object specifies The range of values the object can take Example range 0 to 100 Set of operations that can be performed on the objects Examples and, or, +, -, / 7
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EE4313/EL5493 Standard Data Types All are defined in the STANDARD package (a package is like a library file for VHDL 8
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Enumerated Types type std_logic is ('U' -- uninitialized. Not set to anything yet. 'X' -- unknown. Cannot determine the value '0' -- logic 0 '1' -- logic 1 'Z' -- High Impedance 'W' -- Weak signal, can't tell if it should be 0 or 1. 'L' -- Weak signal that should probably go to 0 'H' -- Weak signal that should probably go to 1 '-' -- Don't care. ); We also need to define the operators for each new type The std_logic type and its operators are defined in IEEE Standard Logic 1164 package. library IEEE;
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This note was uploaded on 11/02/2010 for the course EE 4313 taught by Professor Artansetac during the Spring '10 term at NYU Poly.

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Week02_EE4313_EL5493 - EE4313/EL5493 Lecture 2 N Sertac Artan sartan@poly.edu EE4313/EL5493 Last Week Top-down VHDL-based VLSI design methodology

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