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Week03_EE4313_EL5493_Fall2010

Week03_EE4313_EL5493_Fall2010 - EE4313/EL5493 Lecture 3 N...

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EE4313/EL5493 EE4313/EL5493 Lecture 3 N. Sertac Artan [email protected]
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EE4313/EL5493 LAST WEEK 2
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EE4313/EL5493 Signal Models a physical wire Remember: Variables are updated as soon as a variable assignment statement is executed Signals are updated at a specific time Signals are updated with a (value, time) pair At any time a signal may have associated with several (value, time) pairs force a 16#915FBE41 0, 16#00006355 100, 16#10A9 300 History of values over time, like a waveform If not initialized, default value of a signal is the left-most value of its type (E.g. 'U' for std_logic) <= “ is used for signal assignment 3 (value, time) pairs associated with signal a
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EE4313/EL5493 Conditional Signal Assignment The order IS important The conditions overlap – S0 = '1‘ and S1 = '1' can occur simultaneously 4 -- 4-to-1 Priority Encoder library IEEE; use IEEE.std_logic_1164.all; entity pri_enc is port ( S0, S1, S2, S3: in std_logic; Z: out std_logic_vector(1 downto 0) ); end pri_enc; architecture behavioral of pri_enc is begin Z <= "00" after 5 ns when S0 = '1' else "01" after 5 ns when S1 = '1' else "10" after 5 ns when S2 = '1' else "11" after 5 ns when S3 = '1' else "00" after 5 ns; end behavioral;
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EE4313/EL5493 STRUCTURAL VHDL MODELING 5
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EE4313/EL5493 Structural VHDL modeling If lower level modules are all available, we can assemble them together at a higher level define entities and instantiate them as components Wires (internal signals) are used to inter- connect various components Three key concepts Definition: in separate VHDL files Declaration: before the architecture Instantiation: inside an architecture 6
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EE4313/EL5493 Definition: or_and from Week 1 7 library IEEE; use IEEE.std_logic_1164.all; entity or_and is port ( a, b, c: in std_logic; o: out std_logic ); end or_and; architecture Do_it of or_and is signal D: std_logic; begin D <= A or B; O <= D and C; end Do_it; D A B C O or_and
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EE4313/EL5493 or_andx2 8 A0 B0 C0 D O0 A B C O or_and U0 A1 B1 C1 D O1 A B C O or_and U1 or_andx2 library IEEE; use IEEE.std_logic_1164.all; entity or_andx2 is port ( a0, b0, c0: in std_logic; a1, b1, c1: in std_logic; o0, o1: out std_logic ); end or_andx2; architecture structural of or_andx2 is ???
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