Week05_EE4313_EL5493_Fall2010

Week05_EE4313_EL5493_Fall2010 - EE4313/EL5493 Lecture 5 N....

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
EE4313/EL5493 EE4313/EL5493 Lecture 5 N. Sertac Artan sartan@poly.edu
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EE4313/EL5493 PROCESSES (CONT’D) 2
Background image of page 2
EE4313/EL5493 Process communication What kind of data can be shared in between processes? How about timing? 3 First: Process(a) variable c:std_logic_vector(1 downto 0); begin c := “10”; b <= a and c; end process; Second: process(b) begin a <= not b; end process; Rule of thumb: Use ONLY ONE DRIVER (process) for each signal
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EE4313/EL5493 Inferring Latches If we forget default cases: Final “else” clause in an if -then-else statement The “others” clause in the case statement The simulation will work fine. Modelsim won’t complain ISE Synthesizer (XST) will complain WARNING:Xst:737 - Found 4-bit latch for signal <Y> . Latches may be generated from incomplete case or if statements . We do not recommend the use of latches in FPGA/CPLD designs , as they may lead to timing problems. Unit <IfThenExample> synthesized. Make sure you complete your if-then and case statements Look for latch inference in your synthesis report and make sure you eliminate them before looking for other errors If you infer latches (unintentionally) your circuit will behave in weird ways General rule of thumb: Do not allow a component in your circuit, if you have not designed your circuit to include that component 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY IfThenExample IS port ( X: in std_logic_vector(3 downto 0); Y: out std_logic_vector(3 downto 0); C1,C2: in std_logic); END IfThenExample; ARCHITECTURE behavior OF IfThenExample IS BEGIN L1: process(C1, C2, X) begin if(C1 = '0') then Y <= "0000"; elsif(C1 = '1' and C2 = '0') then Y <= X; else Y <= not X; end if; end process; END;
Background image of page 4
EE4313/EL5493 Area in the Synthesis Report ======================================= * Advanced HDL Synthesis * ======================================= Advanced HDL Synthesis Report Macro Statistics # Registers : 4 Flip-Flops : 4 ======================================= 5
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EE4313/EL5493 Area in the Synthesis Report ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : mux2reg4.ngr Top Level Output File Name : mux2reg4 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 16 Cell Usage :
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 23

Week05_EE4313_EL5493_Fall2010 - EE4313/EL5493 Lecture 5 N....

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online