Week06_EE4313_EL5493_Fall2010

Week06_EE4313_EL5493_Fall2010 - EE4313/EL5493 Lecture 6 N....

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EE4313/EL5493 EE4313/EL5493 Lecture 6 N. Sertac Artan sartan@poly.edu
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EE4313/EL5493 Outline FPGA Architectures Introduction to the Nexys 2 FPGA Board Some simple example designs for Nexys 2 FPGA Board 2
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EE4313/EL5493 FPGA ARCHITECTURES :Modified from Slides by Xilinx 3
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EE4313/EL5493 FPGA Vendors Xilinx Altera Atmel 4
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EE4313/EL5493 Basic Virtex II Architecture On FPGAs, we also have Multipliers Memory Clock Management Blocks Microprocessors High-speed Tranceivers DSP Blocks Etc. I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) Programmable interconnect Overview A closer look 5
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EE4313/EL5493 Configurable Logic Block (CLB) Slices contain logic resources A switch matrix provides access to general routing resources Local routing provides connection between slices in the same CLB, and provides routing to neighboring CLBs CIN Switch Matrix BUFT BUF T COUT COUT Slice S0 Slice S1 Local Routing Slice S2 Slice S3 CIN SHIFT Virtex-II CLB contains four slices 6
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EE4313/EL5493 Slices Slices include Look-up Tables (LUTs) Storage Elements MUXes Carry Logic Virtex-II Slice Slice 0 LUT Carry LUT Carry D Q CE PRE CLR D Q CE PRE CLR 7
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EE4313/EL5493 Look-up Tables (LUTs) Also called Function Generators (FGs) Any 4-input Boolean function can be generated Capacity is limited by the number of inputs, not by the complexity Delay through the LUT is constant Combinatorial Logic A B C D Z A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 . . . 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 8
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EE4313/EL5493 Multiplexer Logic Dedicated MUXes to connect slices and LUTs F5 F8 F6 CLB Slice S3 Slice S2 Slice S0 Slice S1 F7 MUXF8 combines the two MUXF7 outputs (from the CLB above or below) MUXF6 combines slices S2 and S3 MUXF7 combines the two MUXF6 outputs MUXF6 combines slices S0 and S1 MUXF5 combines LUTs in each slice 9
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EE4313/EL5493 Xilinx I/O: The IOB Element Interface between the FPGA and the rest of the world Today many I/O standards exists Different voltages, thresholds Differential or single-ended Etc. IOB supports many of these I/O standards. Spartan Family has less I/O types compared to Virtex Family 10
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EE4313/EL5493 Current Families Virtex-6 FPGAs Spartan-6 FPGAs 150K Logic Cell Device 760K Logic Cell Device Common Resources *Optimized for target application in each family 3.3 Volt compatible I/O LUT-6 CLB DSP Slices BlockRAM HSS Transceivers* Parallel I/O FIFO Logic System Monitor Tri-mode EMAC PCIe ® Interface High-performance Clocking 11
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EE4313/EL5493 Looking into the FPGA: The FPGA Editor After the design is implemented 12
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EE4313/EL5493 Xilinx FPGA Editor 13
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EE4313/EL5493 Xilinx FPGA Editor routes 14
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EE4313/EL5493 Zooming in… Zoom in 15
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