EE4313 - Zhou,HuanXian Homework 4 0225418 EE4313 1. VHDL...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Zhou,HuanXian Homework 4 0225418 EE4313 1. VHDL code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity HW4 is port (clk, rst: in std_logic; in0, in1, in2, in3, in4, in5, in6, in7: in std_logic_vector(7 downto 0); wins0, wins1, wins2, wins3, wins4, wins5, wins6, wins7: out std_logic_vector(3 downto 0)); end HW4; architecture behavioral of HW4 is signal count0, count1, count2, count3, count4, count5, count6, count7: std_logic_vector(3 downto 0); begin process (clk, rst) begin if (rst='0') then count0 <= "0000"; count1 <= "0000"; count2 <= "0000"; count3 <= "0000"; count4 <= "0000"; count5 <= "0000"; count6 <= "0000"; count7 <= "0000"; elsif (clk'event and clk='1') then if ( in0>in1 and in0>in2 and in0>in3 and in0>in4 and in0>in5 and in0>in6 and in0>in7 ) then count0 <= count0 + '1'; elsif ( in1>in0 and in1>in2 and in1>in3 and in1>in4 and in1>in5 and in1>in6 and in1>in7 ) then count1 <= count1 + '1'; elsif ( in2>in0 and in2>in1 and in2>in3 and in2>in4 and in2>in5 and in2>in6 and in2>in7 ) then...
View Full Document

This note was uploaded on 11/02/2010 for the course EE 4313 taught by Professor Artansetac during the Spring '10 term at NYU Poly.

Page1 / 5

EE4313 - Zhou,HuanXian Homework 4 0225418 EE4313 1. VHDL...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online