Homework3_EE4313

Homework3_EE4313 - 2 Test for all possible input – output...

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EE4313/EL5493 1 Homework 3 1. Design a flat, nonblocking 4x4 Switch (each input is 1-bit) with entity name SW4x4Beh 1. Flat hierarchy: A behavioral architecture with no components inside 2. Nonblocking: Any input output pairing should be possible 3. If there are unused cases for the select signal 1. If the select input ever goes to any of these output cases, this is an error and should set all the outputs to 0. 2. Run behavioral simulations on the 4x4 Switch 1. Write a testbench for your behavioral simulations
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Unformatted text preview: 2. Test for all possible input – output combinations with all possible input values 3. Use a for loop in the testbench to test these combinations 4. Test for unused states 3. Place & Route the 4x4 Switch design on FPGA • Deliverables: Your vhdl codes, wave outputs, and PAR Report • Submit Homework 3 by Oct. 12 th to the TA • Demonstrate your simulation to the TA on Oct. 12 th ....
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