Unformatted text preview: 2. Test for all possible input – output combinations with all possible input values 3. Use a for loop in the testbench to test these combinations 4. Test for unused states 3. Place & Route the 4x4 Switch design on FPGA • Deliverables: Your vhdl codes, wave outputs, and PAR Report • Submit Homework 3 by Oct. 12 th to the TA • Demonstrate your simulation to the TA on Oct. 12 th ....
View Full Document
- Spring '10
- TA, Input/output, Cybernetics, nonblocking