hw2 - Zhou, HuanXian 0225418 Design a 2x2 Switch with...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Zhou, HuanXian 0225418 Design a 2x2 Switch with entity name SW2x2. Library IEEE; use IEEE.std_logic_1164.all; entity sw2x2 is port( sel : in std_logic; a,b : in std_logic_vector(3 downto 0); x,y : out std_logic_vector(3 downto 0)); end sw2x2; architecture struct of sw2x2 is begin with sel select x <= a when '1', b when others; with sel select y <= b when '1', a when others; end struct; Simulation Code vlib work vcom sw2x2.vhd vsim sw2x2 view wave add wave * force a 2#0000 0, 2#0001 100, 2#1111 300 force b 2#1111 0, 2#1110 100, 2#0111 300 force sel 1 0, 0 100, 1 200, 0 300 run 400 Screenshot of the simulation: Using SW2x2 components, design a 4x4 Switch with entity name SW4x4
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Zhou, HuanXian 0225418 Library IEEE; use IEEE.std_logic_1164.all; entity sw4x4 is port( sel : in std_logic_vector(5 downto 0); a,b,c,d : in std_logic_vector(3 downto 0); w,x,y,z : out std_logic_vector(3 downto 0)); end sw4x4; architecture struct of sw4x4 is signal int0: std_logic_vector(3 downto 0); signal int1: std_logic_vector(3 downto 0); signal int2: std_logic_vector(3 downto 0); signal int3: std_logic_vector(3 downto 0); signal int4: std_logic_vector(3 downto 0); signal int5: std_logic_vector(3 downto 0); signal int6: std_logic_vector(3 downto 0);
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/02/2010 for the course EE 4313 taught by Professor Artansetac during the Spring '10 term at NYU Poly.

Page1 / 8

hw2 - Zhou, HuanXian 0225418 Design a 2x2 Switch with...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online