Final Project

# Final Project - EL 547 EE 3193 Introduction to Very Large...

This preview shows pages 1–11. Sign up to view the full content.

EL 547 / EE 3193 Introduction to Very Large Scale Integrated Circuits Term Project: 8-Bit Arithmetic Logic Unit Group Members: Byun, ChangEun 0431461 Stanley, Zhang 0435814 Yuan, Zheng 0302740 Zhou, HuanXian 0225418

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Introduction: The purpose of this ALU project is to have an understanding of the complexity and delay issues of logic unit in many of today‟s chips. Following is the basic building block diagrams of our ALU design. Our ALU includes the following logical components: 3 to 6 Decoder, 8-bit OR/EN, 8-bit AND/EN, 8-bit XOR/EN, 8-bit Carry look-ahead ADDER, and a Multiplier. The following is the basic building blocks used in designing the ALU.
3 to 6 Decoder As a simple block the logic for the 3 to 6 Decoder was quickly designed as the following: P 0 = ° 0 ° 1 ° 2 , P 1 = ° 0 ° 1 ° 2 , P 2 = ° 0 ° 1 ° 2 , P 3 = ° 0 ° 1 ° 2 , P 4 = ° 0 ° 1 ° 2 , P 5 = ° 0 ° 1 ° 2 . In implementing this with NAND gates we encountered a large delay of ~40ns, so a faster logic using NOR gates was used which resulting in a measured delay of ~400ps. This is shown in the following simulation tests.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Fig 1. 3 to 6 DCD simulation with S0, S1, S2 pulsing simultaneously; input goes from 8  0 In Figure 1 the input is alternating from 8 and 0 showing that the 3to 6 decoder will only give high output on only the lines that it has and that is selected.
Figure 2. 3 to 6 DCD simulation with S0, and S2 pulsing simultaneously, S2 pulsing inversely; input goes from 5  2 In Figure 2 the input switches between 5 and 2, this gives us the max delay on the critical path (P_5) in yellow and the output when 5 and 2 are selected. What is also shown is the large amount of noise seen on the other lines. The Schematic Diagram of the 3 to 6 decoder, critical path highlighted in yellow. Figure 3.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Layout for 3 to 6 DCD along with pin labels, Figure 4. DRC & Extracted view

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
According to the LVS result, there are 21 p-MOS and 21 n-MOS transistors in this block. It lists all of the nets wired in both layout and schematic. In Figure 4, the layout that was chosen for the decoder was a bit cluttered due to the necessary wiring. A more compact design would be to place the inverters on their side on the left side of the diagram and place the nor gates at the top of the diagram right-side up. Still allowing the GNDs to connect put placing the wiring under the nor gates making things less cluttered. However that would probably take up twice as much space than this design.
Figure 5. 3 To 6 DCD block view symbol Logical Blocks: OR, AND, and XOR 8-bit OR Block Description: This block performs operations of logical XOR for two 8-bit inputs. This block has enable lines for both inputs and outputs. When EN is logic “1” then and only then both inputs and outputs hold correct data.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Complete schematic: There are four sub-blocks in this block. Each sub-block processes two bits. The two pins VDD and GND are present in the complete
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 47

Final Project - EL 547 EE 3193 Introduction to Very Large...

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online