EE3193 VLSI Lab1

EE3193 VLSI Lab1 - EE 3193 Introduction to Very Large Scale...

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EE 3193 Introduction to Very Large Scale Integrated Circuits Lab 1: 3-Input NAND Gate Design Zhou, HuanXian 0225418 Date performed: February 8, 2010 Due date: February 23, 2010 Abstract 1. Schematic 2. Waveform 3. Transient signal simulation and testing Introduction The objective of this lab is to design a 3-input NAND gate using tool Virtuoso Composer. After drawing the schematic of the NAND gate, we should also create the Waveform for the NAND gate and allow a transient signal simulation to verify the functionality of the NAND that was created. Design and Schematic - refer to Appendix I In order to create the schematic of a 3-input NAND gate, we will use the following Instance parts: 3 pMOS4, 3 nMOS4, Vdd, GND, 3 Input pins (A, B, C), output pin (OUT), and wires. 1. The 3 pMOS4 transistor will be connected in parallel. The drain and body will connect to Vdd. 2. The 3 nMOS4 transistor will be connected in series. The source and body will connect to GND 3. The gate of both pMOS and nMOS will connect to the 3 input pins. 4.
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This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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EE3193 VLSI Lab1 - EE 3193 Introduction to Very Large Scale...

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