Lab Tutorial 2

Lab Tutorial 2 - NYU‐Poly Introduction to VLSI Design‐...

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Unformatted text preview: NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Lab Tutorial 2 EL5473/EE3193 ‐ Introduction to VLSI Design Polytechnic Institute of New York University Based on Prof. Mircea Stan's Tutorials at the University of Virginia In this tutorial, we are going to create a layout for our inverter schematic. The Cadence CAD tools we are using in the lab: Virtuoso Schematic Composer for schematic capture. Analog Circuit Design Environment (Spectre) for simulation. Virtuoso Layout Editing for layout. Diva for design rules check (DRC). Schematic with Lambda Rules This time, since we are also drawing the layout, we have to worry about design rules and technology. The technology is the same as for the project and previous tutorials: the TSMC 0.30u CMOS025 5 Metal layers, 1 Poly layer, 2.5 V or 3.3 V supplies, and 0.25 micron minimum feature size. More details about the technology are at: TSMC 0.25 Micron Process Taiwan Semiconductor Manufacturing Company (TSMC) For layout we are going to use the SCMOS_SUBM scalable CMOS design rules for submicron processes available from MOSIS. Please revisit the MOSIS web page for more details about the SCMOS design rules. The TSMC 0.25 micron process uses LAMBDA = 0.15u which seems to be in contradiction with the claim that it is a 0.25u process. LAMBDA = 0.14u is really chosen for satisfying the design rules for everything else except the transistor length. For the transistor length an extra step is done at MOSIS to reduce it from the drawn 0.3u to 0.25u. There are several consequences of using the LAMBDA‐based rules: Transistor sizes (and all other sizes) cannot be arbitrary but need to be multiples of half‐LAMBDA (0.075u) 1 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial The layout grid itself is half‐LAMBDA (0.075u) Check your schematic of your existing inverter and make sure that their sizes are expressed both in microns and in grid units (half‐LAMBDA). The length for example should be 0.3u or 4 grid units. Change the width of the nmos to 4 lambda (8 units) and of the pmos to 8 lambda (16 units). The final schematic should look like this: Check and save and make sure you don't have any errors or warnings. If everything looks fine it is finally time to start layout. Layout with Lambda Rules Since mistakes are common it is a good idea to go now to Options ‐> User Preferences in the icfb window and increase the Undo level to 10: 2 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now, whenever you make mistakes you can simply go back with Undo. Create New CellView First create a layout view of the inverter cell, go to File > New > Cell View… in the library manager and fill in inverter for Cell Name, layout for View Name and Virtuoso for Tool. 3 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Two windows should pop‐up, the Virtuoso layout window screen and the LSW which is used for choosing the layers to be used: 4 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now get acquainted with the Virtuoso layout screen. It is quite similar to the Composer window, important additions being the X and Y absolute coordinates and dX and dY relative coordinates on the top, these are very useful for drawing precise dimensions. The numbers are in microns but notice as you move the cursor that the numbers only change as multiples of 0.075u which is the half‐LAMBDA value and also the grid spacing. The configuration forces a "snap to grid" policy which is very good for enforcing the SCMOS design rules. The entire custom layout is done by drawing rectangles or paths by doing Create > Rectangle or Create > Path and choosing the right layer from the LSW window. Drawing a good layout is more than just drawing rectangles though... The most important aspect is planning: you NEED to use a pencil and paper and make a simple sketch of the layout before you start. You need to decide: the position and orientation of all transistors the orientation and metal layer of the supply lines (vdd and gnd) the orientation and layer of the input and output ports the exact sizes for the transistors and metal lines. 5 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Plan Our Layout We will use a layout that has a similar topology to the schematic. It will have horizontal vdd (top) and gnd (bottom) lines IN on the left and OUT on the right, all in metal 1. All metal 1 lines will be minimum size (3 lambda, or 6 lambda/2 units, 0.45u) except for vdd and gnd which will be 6 lambda wide (12 lambda/2 units). The two transistors will be arranged horizontally. The layout will be made as compact as possible (i.e. use minimum distances as allowed by DRC wherever possible). With these constraints let's start layout! NMOS First let's start with the nmos. We know that the nmos is 4 lambda wide (8 units) which gives us one dimension of the active region. The other dimension can be obtained by adding together all the features that are needed and their minimum sizes according to the design rules: we need the gate (length 2 lambda), two contacts of active to metal1 (2 lambda each), two minimum distances between contact and poly (2 lambda each) and two minimum overlap of active over contact (1 lambda each). If we add all of these together we get a total of 12 lambda. This means that our active region for the nmos is 4x12 lambda. Nactive Let's draw a rectangle 4x12 lambda (0.6x1.8 microns) of nactive (same as active but easier for humans to read) starting from the 0.00,‐1.80 point down and to the right. First click on nactive in the LSW window, then select Create > Rectangle. 6 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Then first click when the absolute coordinates are X: 0.00, Y: ‐0.90, then move until the relative coordinates show dX: 1.80, dY: ‐0.60. Now select Window > Fit All followed by Window > Zoom > Out by 2. 7 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Gate We'll draw another rectangle, 2 lambda wide, in the middle of the active region so that it overlaps the area by two lambda on each side. Click on poly in the LSW and then start from the point X: 0.75, Y: ‐1.80 to X: 1.05, Y: ‐0.60. Contacts Now we need to add the two contacts, both 2 lambda on each side (0.30) and 2 lambda from poly and 1 lambda from the outside. Click on cc in the LSW and then draw the first rectangle from X: 1.35, Y: ‐1.35 to X: 1.65, Y: ‐1.05. 8 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Then copy the rectangle to the position of the other contact by doing Edit > Copy. 9 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Pactive With this the active area for the nmos is done, we still need to put nselect around the active. Before we do that let's define the substrate contact area. Let's draw a pactive rectangle (5 lambda in the X direction and 4 lambda in the Y direction) adjacent to the nmos transistor, then copy a contact into this region. Now we need to surround the active area with select rectangles, nselect for the transistor and pselect for the substrate contact. These areas need to be 2 lambda larger than the active. Nselect Click on nselect first and draw a rectangle from X: 0.00 Y: ‐0.60 to X: 2.10 Y: ‐1.80. 10 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Pselect Then draw a pselect rectangle around the substrate contact. 11 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial NOTICE: In general I suggest you don't look too much at the actual coordinates, many times you can use your eyes and the fact that the cursor snaps to grid to assure correct sizes. For example in the case of the select we know that it needs to be 2 lambda over the active, the same distance as the poly overlap. This can help you to draw the correct sizes without looking at the coordinates. PMOS With this the nmos is complete, we can do the pmos. The pmos is drawn in the same fashion except that nactive becomes pactive and viceversa and nselect becomes pselect and viceversa. Also the width is twice larger and we need two contacts on each side. Notice that we have drawn the nmos with the active area 6 lambda below the Y: 0.00 axis, draw the pmos 6 lambda above the Y: 0.00 axis. You can use copy, stretch instead of drawing some of the shapes to make the layout faster. In the end you should get something like this: 12 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Nwell There is just one more element needed for the transistors: the nwell for the pmos. Draw a rectangle that surrounds the pmos active area by 6 lambda (0.9 microns), you should get: Metal1 We also need to add metal 1 above the contacts that needs to overlap the contacts by 1 lambda. Just do it as below: 13 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial At the end, you will get something like: 14 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Preliminary DRC It is now time to save your design (Design > Save) and run a preliminary DRC. Go to Verify > DRC... Then click on OK. Check your CIW window, you should have no errors, in case you have errors you need to go back and fix them. 15 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Connection Until now we did what is usually called placement, we still need to route our schematic. Output First let's route the output, click on metal 1 and then Create > Path and draw a path from the drain of the pmos to the drain of the nmos (right side). 16 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial The path is only 3 lambda wide(0.45um) so draw it aligned to the right most side. You have to double click to end the path. Now draw another path centered around the 0 axis to the end of the nwell. 17 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Input Now let's connect the input. Draw a poly path between the two gates. Observe that the default width of the poly line is correct: 2 lambda. Now start another poly line centered around the 0 axis going to the left and after you pass the 0,0 point and change to metal 1 by using the Change to Layer in the Create Path window. This should automatically insert a contact between poly and metal 1. 18 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Click once to place the contact structure just to the right of the origin. Double click when you reach the left‐most edge of the nwell to end the path. 19 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial In order to see all the layers in the contact "pcell" type Shift‐F with the cursor in the layout window. You will see: VDD and GND The only items left now are the vdd and gnd connections, we are going to use Create > Polygon for those (we could also use rectangles or paths). Create the polygon using the points: X : ‐0.75 Y : 2.10 X : ‐0.75 Y : 2.55 X : ‐1.65 Y : 2.55 X : ‐1.65 Y : 3.45 X : 2.70 Y : 3.45 X : 2.70 Y : 2.55 X : 0.60 Y : 2.55 X : 0.60 Y : 2.10 Again observe that except for a few of the points you don't really need to look for the actual coordinates since they align with existing structures(well or metal 1). 20 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial The only sizes that you have to worry about are the distance to other metal 1 (e.g. drain) which needs to be >3 lambda and width of the line which we decided to be 6 lambda. For the ground we will simply copy this polygon. First click the previous polygon , go to Edit > Copy and then click on Upside Down in the Copy window. Then click on the polygon again, a upside‐down copy of the polygon will follow your cursor. 21 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now place the copied polygon at the bottom making conatct with the nmos source. 22 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Final Layout DRC Save and run another DRC and make sure you have no errors. Now, we are going to extract the layout of the inverter created earlier, verify that the layout corresponds to the schematic (LVS) and simulate the extracted view with the extra parasitics. Update Schematic and Symbol Before you start preparing our layout, first update the inverter schematic and symbol views such that the vdd! and gnd! terminals are replaced with I/O pins of the type inputOutput named VDD and GND, respectively. First change the schematic by deleting the supplies and replacing them with the VDD and GND inputOutput pins. 23 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial You will have something likes below: When you now run check and save, two warnings will appear. This is because the schematic and symbol no longer correspond. Update the symbol by selecting Design>Create Cellview> From Cellview… in the schematic view. Several pop‐up windows will appear asking if you want to modify the symbol view. Select OK and you will get a symbol of inverter in the symbol view window: 24 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now, delete what you don’t need and move the VDD and GND pins so that your symbol looks the way you want it to. Also, stretch the red box around the symbol to contain all pins and shapes. You can also use the create Line and Add > Shape to finish your symbol. My symbol looks like the following: 25 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial We are making this change because it will help us simulate circuits higher in the hierarchy. In general, you shouldn’t need to do this, but this makes things easier when simulating the extracted view later on. Layout Extraction Open the inverter layout that you created previously. First we’ll do some more "cleanup" of our existing layout. First observe that we can move the metal 1 to poly contact such that we minimize the use of poly for routing. Go to Edit > Stretch and move the contact "flush" with the poly. Merge Now observe that there are many instances where we have polygons and paths that abut each other to make a connection (e.g. metal 1 to metal 1, poly to poly, etc.). This is perfectly OK but takes more memory than if we "merge" them. In order to do that go to Edit > Merge and then click on polygons and paths that can be merged (e.g. start with the output paths, then you can merge the vdd and 26 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial gnd). Notice how they all become as if we had drawn polygons and there are no "lines" artificially separating the regions. Then, you will get: Add pins to your layout When the cleanup is done we can prepare for extraction and LVS. In order to be able to do that we have to define the input and power supply pins in our layout as in the schematic. Go to Create > Pin and enter IN as Name, input as I/O type and metal1 as Pin type. 27 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Place the pin on the leftmost side of the metal 1 shape used as an input. Simlarly place an output pin OUT on the right most end of the output metal 1 polygon and two inputOutput pins called VDD and GND for power and ground on the respective metal shapes on the top and bottom of the layout. Notice the 4 squares that represent the pins in the layout. Go to Verify ­> DRC... and make sure you have no design rules errors. Extract Now we can extract the layout. Go to Verify ­> Extract... Click Set Switches in the pop‐up window and choose Extract_parasitic_caps. 28 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial 29 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Notice that here you could have generated pselect and nselect layers automatically, you may decide to do that in the future to save some effort. Now click on OK. In the icfb window make sure you have no errors. If there are no errors you can now open the newly created extracted view from the Library Manager by double clicking it. This opens another layout window only with the extracted view. 30 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial In the extracted view window, press Shift‐F to see the symbols for the extracted transistors. Notice that the extracted view is a layout that also includes an underlying schematic. 31 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Layout VS. Schematic (LVS) Now in the extracted window go to Verify > LVS... The following window should pop up. If another window comes up in addition to the one below, click Run and wait until the stop window pops up. While running, you will see the message “LVS job is now started...” in the icfb window. If the LVS runs successfully, you will see: The stop window that pops up simply signifies that LVS has terminated, not that the comparison was successful. Click OK. In order to see that LVS verified that the layout corresponds to the schematic, click on Info in the LVS window.. 32 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now we can finally verify. Click on Output and check to see that "The net‐lists match" statement is made somewhere in the file that pops up. If you are curious, you can also click on Netlist for the schematic and/or extracted and see what those look like. 33 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Simulation of Extracted View We are almost done. The only thing left to do is simulate the extracted view of the inverter including the associated parasitics. This simulation will more accurately predict the behavior of the circuit when fabricated in silicon. Since our cell layout is very small it is likely that the parasitics are so small that no significant simulation differences will be observed, but in general the differences can be substantial for large complicated layouts. First, you need to create a symbol for your cell, in case you don't already have one, using Design > Create Cellview > From Cellview in the schematic window. Then create a new cell schematic called "testbench". Open testbench, click Instance shortcut on the left, choose the Library EL5473 (the one contains your inverter ), click on inverter, and Hide. 34 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Place your inverter symbol and you will get: 35 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Add input and output ports and supply symbols (vdd and gnd). Vdd and gnd need only be placed at the top level, no need to connect them to anything else. Now let's start Analog Environment, in the newly created "testbench" schematic cell window go to Tools > Analog Environment. In the Analog Environment window go to Setup > Environment. 36 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial The line that we need to change is labeled Switch View List. This entry is an ordered list of cell views that contain information that can be simulated. The simulator (in fact the netlister) will search until it finds one of these cellviews. The default entry does not list an extracted cellview. We need to add the entry for the extracted cellview in front of the schematic cellview. As a result of this modification, the simulator will use the extracted cell view of the cell for simulation, if one is available. Click OK. 37 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial With Analog Environment setup to simulate using the extracted view, run the same transient simulation as you ran in tutorial 1. The simulation results for signal OUT should look like that shown below. Typically, you will want to compare such extracted view results to simulations of the more ideal schematic. For the inverter, however, the differences should be negligible. With that, you have completed the second tutorial. Congratulations! 38 ...
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