Lab Tutorial 3

Lab Tutorial 3 - NYU‐Poly Introduction to VLSI Design‐...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Lab Tutorial 3 EL5473/EE3193 ‐ Introduction to VLSI Design Polytechnic Institute of New York University Based on Prof. Mircea Stan's Tutorials at the University of Virginia In this tutorial, we are going to create a schematic of hierarchical ring oscillator by using symbols for lower level schematics. The Cadence CAD tools we are using in the lab: Virtuoso Schematic Composer for schematic capture. Analog Circuit Design Environment (Spectre) for simulation. Symbol Creation First we need to create a symbol for the inverter schematic that we created in Tutorial1. If you haven’t done so, please take the following steps to create your own symbol. Open the schematic view of the inverter in library EL5473 by double clicking on it. There are two possibilities for creating a symbol: create the symbol from scratch or edit an existing symbol. To create a symbol from scratch you do that in Virtuoso Schematic by going to Design > Create Cellview > From Cellview which brings up a dialogue box (below) with default settings from schematic to symbol. 1 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial From this dialog window you can create a default inverter symbol. The only disadvantage with this method is that the default shape is a box and you would need to change that (no big effort really). Click OK. If a window pops up entitled “Overwrite Base Cell CDF,” just click YES. A new Virtuoso window will pop up with a box as the symbol view. Now, delete what you don’t need and move the VDD and GND pins so that your symbol looks the way you want it to. Also, stretch the red box around the 2 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial symbol to contain all pins and shapes. You can also use the create Line and Add > Shape to finish your symbol. My symbol looks like the following: Hierachical Schematic Capture Now we can create a hierarchical schematic that uses the symbol just created. Go to the Library Manager and with the EL5473 library highlighted and select File > New > Cell View to create a new schematic view named RingOsc. The Composer schematic editor window should open up. We will create a schematic of a ring oscillator with 11 inverters. Click on instance button and choose the symbol view of the cell inverter in the EL5473 library. We are going to place 6 inverters first and we can do that with just one command by filling the Array inputs, let's say Rows 1 and Columns 6 (all 6 inverters will be arranged horizontally). 3 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now click once to place the left most inverter, then move the mouse to the right and click again to place the remaining ones. If you make a mistake you can always do Edit > Undo and try again. Now, you will see something like: 4 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Press ESC. Now we need to place the other remaining 5 inverters but they need to face left. For this we do again place instance with 1 Row and 5 Columns but before we place the inverters we need to click twice on the right mouse button, this will rotate the inverter symbol by 180 degrees. Then click the left mouse button once for the right most inverter, then move the mouse to the left and place the remaining inverters. Don't be afraid if you make mistakes, just Undo and start over. Now we only need to wire the 11 inverters into a ring and add a vdd and a gnd symbol from the NCSU_Analog_Parts > Supply Nets. Run Check and Save and make sure you have no errors or warnings. Your final schematic should look something like the one shown below. 5 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial NOTICE: There is one thing that you need to pay attention to. In this design, I use the InputOutput type as the VDD and GND in the basic inverter. As below: Pin type: InputOutput If you are also using this, just follow the above steps to finish your RingOsc. In fact, you can also do it in another way. If you choose to use NCSU_Analog_Parts > Supply Nets as your VDD and GND type, you will get your inverter like this: 6 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial You should also create your symbol as we just discussed. And your symbol will look like: You may notice that in this case, your symbol has no VDD and GND pins. Because they are recognized as supplies by the software rather than pins, so when you use this symbol, you only need to connect the input and output, and add the VDD and GND from NCSU_Analog_Parts ‐> Supply Nets and leave them unconnected on the top. Your RingOsc will as below: 7 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Both the designs are correct. However, each of them has pros and cons, you may make your own choice before starting your design. Traversing the Hierarchy Many times when you have a complex hierarchical schematic you may want to make modifications on different cells without having to close and open different windows. You can do that by traversing the hierarchy. You can traverse both up and down, for example you can go down from the RingOsc schematic and make modifications in the inverter schematic, then go back up the hierarchy. To do that you have to click on a single inverter symbol that you want to descend to (in the Virtuoso Schematic window), then go to Design > Hierarchy > Descend Edit. 8 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Then click OK on the pop‐up dialog box. The schematic of the inverter should now appear in the schematic window. 9 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now you can edit the inverter (if you want), then check and save. This will change all inverter instances in your hierarchical schematic. We don't really need to make any changes now. For now let's just go back up by clicking Design > Hierarchy > Return. You should now see your RingOsc schematic. Simulation First we will perform a transient simulation to see that our inverter ring works correctly. In the Virtuoso Schematic window go to Tools > Analog Environment. The design should be set to the correct Library, Cell and View. As in Tutorial1, we first need to set up the power supply. Go to Setup > Stimuli. In general you have to set up Inputs and Global Sources, but in this case we don't have any explicit inputs. We only need to setup the global sources (power supply) since there are no other inputs or outputs for the ring oscillator. Click on the Global Sources, you should have only one (vdd!). Click on Enabled, Function dc, Type Voltage, DC voltage 2.5, Source type dc, and click on Apply. The vdd! should turn from OFF to ON. 10 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Click OK. Now you need to choose the type of simulation, go to Analyses > Choose... In this case we will choose tran which is the default, 4n as the Stop time and moderate as the accuracy default. Now go to Outputs > Save All to make sure allpub is checked for signals to save. 11 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Click OK. CAUTION In general, once you have a big schematic, you will want to only save a few signals for simulation, this will make your simulation faster. For small circuits as we have now it doesn't make a big difference though. In order to help with convergence we can also set up some initial conditions, for example make the left‐most node a zero. Go to Simulation > Convergence Aids > Initial Condition. Then click on the left most node in the schematic. A big zero should appear on top of the net. Click OK. 12 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Now we can finally simulate! Click on the Netlist and Run button (looks like a green light) on the right or go to Simulation > Netlist and Run. In case you have errors you will need to go back and correct them. This can be tricky! You may need to do Simulation > Netlist > Recreate if you change the schematic. NOTICE: Each time you change the schematic you have to do Check and Save! Assuming there are no errors you can now admire the simulation results. Go to Results > Direct Plot > Transient Signal which will pop‐up your schematic window. Now you have to click on the signals you want to see. Since this is a transient analysis we want to see a few voltages. In order to do this you have to click on the desired nets, then the ESC key (try not to choose the signal with the initial condition of 0 since the transient there may be worse than on the other inverters). Here, I choose the three signals on the schematic: You should finally get the desired simulation results, some glorious periodic signals as expected from a ring oscillator. You can determine the period of oscillation, measure the inverter delay and compare that with what we learned in class. 13 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial You may click on the Strip Chart Mode to separate each wave. Now we can measure tpdf, tpdr, trise, tfall for the inverters. To do this accurately we are going to use the waveform calculator. Go to Tools > Calculator in the Analog Environment window which should pop up the calculator. 14 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Find the item delay in the right bottom window and click on it. You will see the delay calculation window: 15 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Familiarize yourself with the delay calculator; you may also want to consult Help or cdsdoc. The calculator works when you first input one or more operands (waveforms) and then you perform an operation on them. After each operation it's recommended that you clear the stacks. When you want to calculate delay, choose the two signals that you want to compare and specify the edge and the threshold value and click evaluate. Remember click on the wave button in the calculator before load the wave. For example, let’s calculate the trise of the first inverter. From the lecture, we know that when we input a falling signal, the output of inverter will take some time to go up. The trise of inverter is the time that the output rises up from 20% of the full voltage to 80% of the value. So, we should choose the output waveform of the first inverter, that is, the first wave‐net42. Click the signal 1 in the calculator window and click on the first wave in the waveform window, and you will see that you have already loaded your signal. Then choose the same signal for signal 2 because we are going to determine the rising delay of it. Type in 0.5(that is 20% of 2.5V) for threshold Value 1, 2 under Edge Number 1(the first rising edge of inverter 1), 2.0(that is 80% of 2.5V) for threshold Value 2, 2 under Edge Number 2. Leave other items unchanged and click Apply at the bottom. 16 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial Then, click Eval. You will get your result. 17 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial If you want to calculate the tpdr of the second inverter, make the following changes in the window: 18 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial 50% falling Input point Net42 50% rising Output Net38 Net42 Net38 Inverter 2 Click Apply and Eval, you will get your tpdr of your second inverter. (You may have different wire names from mine. Those numbers are just for better interpretation. ) 19 NYU‐Poly Introduction to VLSI Design‐ Lab Tutorial You can use these delays to estimate the delay of 11 inverters ring and then determine how fast your ring oscillator will be. It is a good idea to save your state before exiting the simulator in case you want to redo some of the simulations you can start by loading a saved state. 20 ...
View Full Document

This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

Ask a homework question - tutors are online