Lab Tutorial 4

Lab Tutorial 4 - NYU-Poly Based on Prof. Mircea Stan's...

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NYU-Poly Introduction to VLSI Design- Lab Tutorial 1 Lab Tutorial 4 EL5473/EE3193 - Introduction to VLSI Design Polytechnic Institute of New York University Based on Prof. Mircea Stan's Tutorials at the University of Virginia In this tutorial, we are going to draw a D-Latch starting with the inverter we created in the previous tutorials. This tutorial will revisit hierarchical schematic entry but will build on that by introducing hierarchical layout design. The Cadence CAD tools we are using in the lab: Virtuoso Schematic Composer for schematic capture. Analog Circuit Design Environment (Spectre) for simulation. Virtuoso Layout Editing for layout. Diva for Design Rules Check (DRC). Diva for extraction. Diva for Layout vs. Schematic Check (LVS). Since we will modify the inverter created in previous tutorials it is a good idea to make a copy. Do this by highlighting inverter under the Cell column of your library manager, right click it and select Copy. .. from the appeared pull down menu. Change the name of the Cell in the To box to INVX1. Click OK and you will get an identical cell including all the views with the name INVX1.
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NYU-Poly Introduction to VLSI Design- Lab Tutorial 2 Following similar steps to create the inverter schematic in Tutorial 1, we will now create a simple transmission gate. Start by creating a new schematic cell view in the library manager named XGATE. Draw your transmission gate schematic to look like that shown below. The NMOS and PMOS transistors are sized to 600nm and 1200nm, respectively.
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NYU-Poly Introduction to VLSI Design- Lab Tutorial 3 Click Check and Save to save your design and make sure that you have no error.
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This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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Lab Tutorial 4 - NYU-Poly Based on Prof. Mircea Stan's...

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