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Lab1 - Fix any problems that might exist You cannot move on...

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EL 5473 Introduction to VLSI Design Lab Assignment 1 Due beginning of Class February 23, 2010 Before starting the lab itself, complete Tutorial 1 – you may want a TA to check that it has been completed successfully. 1. Design a 3-input NAND gate including transistor sizing and draw your schematic using Cadence Virtuoso Composer. NOTE: This circuit is to be implemented using the TSMC 0.3 um technology file. If you create your cell in the EL5473 library created in the tutorial then this is automatic. From here on, all designs are to be implemented using the TSMC 0.3 um technology unless otherwise specified. 2. Check and Save your design.
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Unformatted text preview: Fix any problems that might exist. You cannot move on unless Check and Save passes with no errors. 3. From the Composer window, open Analog Environment and set up the input waveforms and global signals (vdd). The inputs should be set as pulse waveforms with a period of 2ns and slope of 50ps. You can refer to Tutorial 1 as an example how to set up the waveforms. 4. Enable a transient simulation ending at 8ns. Run the simulation and plot all 3 inputs and the output of the gate. Verify the functionality is that of a 3-input NAND gate. 5. Deliverables: a. 3-input NAND gate schematic b. Waveform for functionality verification....
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