EE3193 VLSI Lab2

EE3193 VLSI Lab2 - EE 3193 Introduction to Very Large Scale...

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Introduction to Very Large Scale Integrated Circuits Lab 2: 3-Input NOR Gate Design Zhou, HuanXian 0225418 Date performed: February 23, 2010 Due date: March 2, 2010 Abstract 1. Schematic 2. Layout 3. DRC result Introduction The objective of this lab is to design a 3-input NOR gate schematic, then draw its layout, and verify with DRC result to ensure an error free design. Design and Schematic In order to create the schematic of a 3-input NOR gate, we will use the following Instance parts: 3 pMOS4(w = 1.2 u m, l = 300 n m), 3 nMOS4(w = 600 n m, l = 300 n m), Vdd, GND, 3 Input pins (A, B, C), output pin (OUT), and wires. 1. The 3 pMOS4 transistor will be connected in series. The drain and body will connect to Vdd. 2. The 3 nMOS4 transistor will be connected in parallel. The source and body will connect to GND 3. The gate of both pMOS and nMOS will connect to the 3 input pins(A, B, C). 4.
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This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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EE3193 VLSI Lab2 - EE 3193 Introduction to Very Large Scale...

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