HW1-Solution

HW1-Solution - ≈ 20 billion Clock speed estimation based...

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EL 5473 Introduction to VLSI Design Homework Assignment 1 Solution 1. Explain what is Moore’s Law. Based on the evolutionary trends described in chapter 1, predict the integration complexity and the clock speed of a microprocessor in the year 2020. Answer: Page 4 in text, Moore observed in 1965 that plotting the number of transistors that can be most economically manufactured on a chip gives a straight line on a semi-logarithmic scale. At the time he found transistor count doubling every 18 months. Intel microprocessors have double transistor number every 26 months (~2 years). Integration complexity estimation: based on Fig 1.4 in text, transistor # is ~ 20 million in 2000. Transistor # doubles every 2 years. Then transistor # in 2020 will be 20 million * 2^ (20 years /2 years) = 20 million*2^10
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Unformatted text preview: ≈ 20 billion. Clock speed estimation: based on Fig. 1.5 in text, clock freq. in 2000 was close to 1GHz. Clock frequency doubles every 34 months. Then clock frequency in 2020 will be 1GHz * 2^(12*20 months / 34 months) ≈ 1GHz*2^7 ≈ 128GHz. 2. (Problem 1.3 in text) Sketch a transistor-level schematic for a CMOS 4-input NOR gate. VDD OUT A B C D 3. (Problem 1.6 in text) Sketch a transistor-level schematic of a CMOS 3-inpt XOR gate. You may assume you have both true and complementary versions of the inputs available. 4. Draw layout and cross-section for a PMOS transistor in an n-well process that has active, p-select, n-select, polysilicon, contact, and metal 1 masks. Include the well contact to VDD. V DD Y A well tap pMOS transistor p+ n well Y V DD n+ well tap p+...
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This note was uploaded on 11/02/2010 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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HW1-Solution - ≈ 20 billion Clock speed estimation based...

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